Font Size: a A A

Key Techniques Of On-chip Trace Debug And Fault Detection For Embedded Multi-core Processor

Posted on:2008-06-04Degree:DoctorType:Dissertation
Country:ChinaCandidate:X HuFull Text:PDF
GTID:1118360242999235Subject:Microelectronics and Solid State Electronics
Abstract/Summary:PDF Full Text Request
With the flourishing development of the embedded system industry, more and more attentions are paid to efficient development and debugging tools. On-chip trace technique records run-time information of the processor with dedicated hardware non-intrusively. Without code changes, on-chip trace has the advantage of high reliability and does not affect the run-time behavior of the system. It is able to overcome the debug obstacle of current embedded systems with high level of integration and high real-time requirements. Therefore on-chip debug becomes an important research aspect of debug technology in recent years.In aerospace and military applications, the reliability of processors becomes a critical issue. Therefore fault-tolerant mechanisms are required to deal with hardware failures. Error detection is the first step in the fault tolerance. Meeting the cost and power requirements of embedded systems, the study on the error detection with low hardware cost and low performance loss is of great significance.In this dissertation, on-chip trace debug and on-line error detection are studied. We first discuss the debug model of embedded processors, and give an in-depth analysis on the principles, advantages and realizations of on-chip trace technique. And then we study three aspects: the collection and compression of run-time information, the transmission structure of trace data and the debugging and optimization assisted by trace. A multi-core on-chip trace system is founded to verify the conclusions mentioned above. This dissertation also presents a control-flow error detection method for the low-cost requirements of fault tolerance of embedded processors.Primary innovative works in this dissertation can be summarized as follows:(1) We propose several innovations and improvements on trace information collection and compression to improve the compression ratio and flexibility. A Long and Short Chart Encoder is presented that can compress the trace data of conditional branches effectively. Configuration bits of branching output are designed that can achieve a flexible tradeoff between trace contents and data volumes. Event trace is implemented that can assist optimization effectively, and the encoding method for event trace can achieve a good tradeoff between accuracies and volumes. We also present a NOP_config instruction that can configurate the on-chip trace hardware non-intrusively.(2) Scheduling for combining the traffic of multi-source trace data is one of key issues that affect the performance of trace data transmission. By analyzing the features of trace traffic combination, a lazy scheduling algorithm based on the service threshold and the minimum service granularity is proposed. The queue length distribution is constrained by configurable service threshold of each queue, and switching overheads are reduced by lazy scheduling and configurable minimum service granularity. Simulation results show that the algorithm controls the overflow rate of each queue effectively and utilizes the buffer capacity sufficiently according to the queues priority assigned. The algorithm has good scalability with reasonable hardware costs.(3) Expanding the application of on-chip trace debug, a method combining code layout and instruction prefetching is proposed. The program execution path with timestamps is offered by on-chip trace non-intrusively. By exploring the phase behavior of program execution path, code layout is executed for maximizing the prefetching intervals, and prefetching operations are executed by unoccupied function units in the VLIW architecture. Simulation results show that instruction cache misses are much reduced compared with code layout or instruction prefetch implemented alone.(4) Focusing on low-cost fault detection for embedded systems and characters of the VLIW architecture, a hybrid control flow checking method (V-CFC) by monitoring signatures is proposed. Signature instructions with weak position constraint are designed to offer the redundant control flow information, and these instructions can be executed in unoccupied instruction slots or in positions of NOP instructions to minimize the overhead on processor performance and program code size. Dynamic Offset Signature Instructions are proposed to offset the expected signature by accessing branch registers in run time, therefore V-CFC expand the error detection scope compared with other hardware methods and reduce the performance loss compared with a software method. V-CFC is able to check bit flips of instruction codes and 15 types of execution sequences control flow errors with the high error-detection coverage, low performance loss and low hardware costs.(5) A debug model of embedded processors is founded with the state set of storage elements, and an in-depth analysis is given on the principles, inherent advantages and realization models of on-chip trace. An on-chip trace system is founded on the platform of a multi-core processor YHFT-QDSP. A case study to a multi-core program shows, the system is able to assist debugging and optimization effectively.
Keywords/Search Tags:Embedded System, Multi-Core Processor, Digital Signal Processor, Multi-Core Debug, Debug Model, Non-intrusive Debug, On-chip Trace, Scheduling, Code Layout, Instruction Prefetch, Fault Tolerance, Control Flow Error Checking
PDF Full Text Request
Related items