| Evolvable Hardware (EHW) refers to hardware that can change its architectureand behavior dynamically and autonomously by interacting with its environment.Theprime motivation of EHW is to simulate the nature of evolution on a reconfigurablehardware platform.EHW have a wide range application prospects at circuit design,autornatic control,fault-tolerant systems,artificial intelligence,robotics,and deepspace exploration.First,the purpose of this dissertation is to study circuit design methodology baseon EHW,on the two aspects:gate-level and function-level FPGA-based hardwareevolution.In the gate-level field,A LUT-based VRC implementation of EHW hasbeen proposed with the aim to find a general purpose VRC model for evolvingrandom logic function targets.Experiment results indicate that 3-LUT based VRCachieves the best results,and gets a significant improvement in resource utilization ofthe basic cell.In the function-level research,a new architecture of EHW cell has beenproposed for image filter,the filter evolved from this architecture can successfullyfilter out Gauss noise and Salt-and-pepper noise.Second,aims the drawbacks of the existing FPGA-based EHW platform,anSOPC chip based on CPU+FPGA was designed and implemented on 0.13um logicprocess.The SOPC chip was designed to speed up the hardware evolution processfrom three aspects.First of all,because only a small mount of bitstream changes inthe every evolution iteration,a row-column dual-decode architecture is adapted tospeed up configuration.Compared to the traditional row based architecture,thismethod reduces the smallest bitsteam scale and significantly improves the speed ofpartial configuration.Next,a dedicated CPU configuration interface is designed,enable CPU to configure FPGA conveniently and realize on-chip evolution.At last,genetic algorithm needs much of random numbers,in this chip,a dedicated randomnumber generator and cross-accelerator is designed in order to achievehardware-accelerated genetic algorithm.
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