Font Size: a A A

Ofdm Systems, High Performance Ldpc Decoder Realization

Posted on:2011-10-31Degree:DoctorType:Dissertation
Country:ChinaCandidate:B XiangFull Text:PDF
GTID:1118360305497208Subject:Microelectronics and Solid State Electronics
Abstract/Summary:PDF Full Text Request
With rapid developments of multimedia broadcasting, celluar communication, and VLSI technology, mobile users and services grow at an exponential rate.The next generation of communication system must feature large capacity, high speed, and lower power. Due to changing radio environments and diverse standards, multi-mode configurable mobile terminals are in demand. To insure reliable transmission, FEC codes get fast developments and wide applications. LDPC code, close to Shannon limit, is widely applied in the DVB-S2, DTMB, CMMB, WLAN, WiMAX, etc. Therefore, designing high-performance LDPC decoder is now one of the hotspots.Due to mass parallel computing, memory read-write accesses, and register overturns, high-speed LDPC decoders feature high power and large area. Improving parallel degree results many problems, such as data dependency, configurability, memory access conflicts, etc. Based on different applications, the dissertation designs several LDPC decoders, solves the problems from high parallel degree, optimizes their power consumption and area, and boosts their configurability. The main contributions of the dissertation include the following aspects.With key techniques of speeding up decoding convergency, two-phase fully overlapping, dual-path parallel computing, and deep pipelining, the decoders' throughputs are improved further. With key techniques of memory access reduction, dynamic clock gating, early termination strategy, and parallel and pipelining, the decoders'powers are lowered further. With key techniques of computing complexity and memory resource reduction, memory structure optimization, and utilization ratio improvement, the decoders'areas are much smaller.Based on the study of the above key techniques, four decodersâ… ,â…¡,â…¢, andâ…£with different parallel degrees are designed and implemented. Decodersâ… andâ…¡attain about 100Mb/s and are fit for the multimedia broadcasting systems:DTMB and CMMB; Decodersâ…¢andâ…£attain>250Mb/s and are fit for the high-speed celluar mobile communication system:WiMAX and 4G. All the key techniques and methods are tested and verified in the decoder chips.
Keywords/Search Tags:CNU, CWSR, Decoder, Dual-path parallel computing, FEC, Memroy partition, Matrix transformation, QC-LDPC, Read-write bypassing, Reordering of nonzero sub-matrices, RWSR, Symmetrical pipelining, Two-phase folly overlapping, VNU
PDF Full Text Request
Related items