Modeling And Application Research Of On-chip Multilayer Inductors

With the development of the advanced deep sub-micron CMOS process, on-chip inductors become one of the most indispensable devices for integrated radio frequency and high speed transceivers, and are used intensively in the design of circuit modules. Because more process and design supports are available, the planar inductors are preferred in normal cases. The main disadvantage of planar inductor is large area occupation which increases cost. As the CMOS process advances, more metal layers are available which provides sufficient conditions for the design of multilayer inductors. Although it’s not always true, the performance of multilayer inductors is considered inferior compared with planar inductors. Moreover, the multilayer inductors have complicated and irregular structures, and lack process and design support. Hence, the researches and applications of multilayer inductors are less than that of planar inductors.Though there are many problems on the practical applications of on-chip multilayer inductors, it is still attractive and meaningful to use them due to large amount of chip area saved. With the emphasis on application, the characteristics of various types of multilayer inductors are analyzed, and also some critical issues about the design of circuits and inductors are investigated in this dissertation. The main contents are as following:1. The basic physical features of multilayer inductor are discussed. Based on the common parameter definitions and structure analysis of multilayer inductor, the basic physical parameters and circuit model is derived, which includes series inductor, series resistor and parallel capacitor. The analytical calculation models for each element are built. For series inductor, the Greenhouse method with the extension on the calculation of geometrical mean distance for multilayer inductor is applied. For series resistor, a new method to calculate the eddy current inductance is proposed to increase the accuracy and extend valid frequency range of previous models. For parallel capacitor, the distributed capacitance model is applied.2. The modeling of skin effect, proximity effect and substrate effect is discussed, and the lumped and the distributed models are analyzed. From basic circuit model, in consideration of the characteristics of multilayer inductor and requirement of design and application, a lumped single-π equivalent circuit model with lateral substrate coupling resistor is determined. Compared with the previous complicated and dedicated models, the simple and general model is more advantageous for the application and circuit design of multilayer inductor. Also, the method for model parameter extraction and de-embedding of measurement are given.3. The physical meaning of quality factor of on-chip inductor is discussed from energy perspective. Several impact issues and optimization methods about quality factor are addressed, including multiple metal layers stacking, distance of ground tapping, patterned ground shield and metal width tapering structure. Based on the analytical calculation model of series resistance and physical meaning of quality factor, with the ratio of dc inductance over ac resistance as the criteria, a new optimization algorithm for metal width tapering structure is proposed.4. Four circuit design examples with multilayer inductors are given, including5GHz/10GHz dual-mode voltage controlled oscillator, dual-/triple-band switched-inductor voltage controlled oscillator,5.8GHz low noise amplifier and2.4GHz up-conversion mixer. The detailed design process of choosing the inductor type and determining the geometrical parameters of multilayer inductors is demonstrated, and also the simulated or measurement results are given. The practical circuit designs verify the applicability of on-chip multilayer inductors and the significant effectiveness to reduce chip area and cost.