Reasearch Of Power Integration In Soc Based On Digital Assistant Technology

In nowadays, SoC (System on Chip) is playing an important role in personalinformation devices. For higher level integration, extral power management integratedcircuits are becoming on-chip integration. Traditional power management ICs are basedon analog control, facing lots of challenges in advance technologies. In contrast, digitalcircuits perform better process compatibility and signal processing capability. Thedissertation focuses on Digital Assistant Power Integration (DAPI) technique, mainlyabout digital assistant DC-DC converter, digital controlled DC-DC converter, PMU(Power Management Unit) and PMU integration in SoC. Solutions are proposed torealize highly precise, high level integration and high efficiency power integration. Theresearches and innovations consist of:(1) Digital error correction scheme in DC-DC converters is proposed. Given lowloop gain and bad regulation in phase lead compensation, compensation current is addedat output of error amplifier. Two comparators are designed by reusing output current oferror amplifier to detect whether output in tolerance range. Finite stage machine is usedto adjust compensation current. Regulation and output precision are greatly improved.DC-DC converter based on digital error correction is good combination of analog anddigital control schemes, performing good regulation, low error and fast response,suitable for DVS (Dynamic Voltage Scaling) systems. The output error is within10mVin load and25mV per step DVS range. The DVS speed are30μs and32μs for up anddown reference tracking, respectively. Because of small passive devices of phase leadcompensation, the converter is monolithically integrated and can be integrated in PMUwith small area.(2) A self calibration scheme for DPWM (Digital Pulse Width Modulator) isproposed. The reasons of degeneration of linearity in DPWM are analyzed. Based onlimiting different of delay cell control words, linearity is improved by combination ofdelay cells with different delay. Full digital2MHz10bit implementation realizes highlinearity. After calibration, the INL and DNL are reduced from-5.1to1.3and from5.1to0.4, respectilvely. Full digital DPWM is compatible and convenient with different process. It provides good choice for digital controlled DC-DC converters with muchhigher precision outputs.(3) Design and realization of conversion efficiency improvement techniques. Inorder to improve conversion efficiency, multi digital methods are used to enhanceoperation of power converter, including dual mode operation, adaptive power transistorsizing and adaptive dead time control. By using variable techniques, light load currentconsumption is reduced and efficiency in wide load range is improved. The dead timedetector proposed in the dissertation detects body diode conduction of power device.Logic is triggered by flip edge of detector output. N type power device is then opened,achieving minimum dead time. Comparing to other implementations, the proposedadaptive dead time control circuit performs faster response and better robustness. Thetechniques are used in a2MHz DC-DC converter and the peak efficiency is91%andabove80%at light load.(4) Design and realization of digital controlled dual mode DC-DC converter:differential oscillator based ADC with small area, high conversion precision, goodprocess and temperature stability is realized by dealing with differential input of ADC infrequency domain. Digital compensator is built to compensate the converter by buildingIIR (Infinite Impulse Response) filter. The converter operates in PWM mode with heavyload and PSM mode with light load. High conversion efficiency is realized in wide loadrange.(5) Design of PMU with dual DVS ability: Multi phase clock and substrate noiseisolation are used to improve stability and compatibility in PMU with several switchingDC-DC converters. In order to achieve fast and efficient DVS response, maximumcharging control and PSM control work together.(6) Integration of PMU in a low power SoC: The chip functions well. A novel AVSarchitecture is given to further overcome the shortages of DVFS system. The novel AVSarchitecture can realize optimum supply voltage under different process, temperatureand voltage variations, enabling minimum power consumption of SoC.