The Study On Single Event Effects In Flash-based FPGAs And The Design Of New Single Event Effects Test System

The aerospace industry at home and abroad has made considerable progress due to human space flight and exploration, however, single event effects(SEEs) induced by space radiation are the key factor threatening the satellites safety in space environment. So how to keep the satellites safe has been a growing issue in modern spacecraft design. With the continuous improvement of space mission requirements, Field Programmable Gate Arrays(FPGAs) are widely used in the field of spaceflight. Consequently, the SEEs of FPGAs have been a major concern. The Heavy Ion Research Facility in Lanzhou(HIRFL) is an effective instrument to study the SEEs, so it will be the future developing trend in the domestic and international to study the SEEs using heavy ion accelerators.In order to study the heavy ion single event effects of the FPGAs, the flash-based FPGAs manufactured by Microsemi are selected as the research object. Two different test methods for Versa Tiles and BRAMs are designed. Then the experimental tests were carried out using the SEE test platform developed in-house based on the HIRFL. The relation between the cross section and different linear energy transfer(LET) values for Versa Tiles and BRAMs is obtained. The experiment results show that there is no too much dependence on the sequential logic cross section with the device’s operating frequency. And the relationship between 0�'1 upsets(zeros) and 1�'0 upsets(ones) is different for different kinds of D-flip-flops(DFFs).Then the error correcting codes(ECCs) mitigation for BRAMs are study based on the heavy ion experiments. Two different ECCs, the shortened Hamming codes and shortened BCH codes, are investigated in this paper. The concrete design methods of the codes are presented. Also, the codes are both implemented in flash-based FPGAs. Finally, heavy-ion experiments are performed, and the experimental results indicate that the error cross-section of the device using the shortened Hamming codes can be reduced by two orders of magnitude compared with the device without mitigation, and no errors are discovered in the experiments for the device using the shortened BCH codes.Finally, a new SEE test system using the structure of “So C + FPGA” is designed based on the existing test system. The new device Zynq-7000 manufactured by Xilinx is adopted and it will make the system more flexible. The new test system can provide 120 single-end and 40 pairs of differential signals, support many kinds of standard level. Therefore, many devices under test(DUTs) can be tested using this test system. At last, the new test system is verified successfully using the method of fault injection under laboratory conditions.