The Development Of Front End Trigger Electronics Prototype System In ATLAS LAr Calorimerers Phase-I Upgrade

ATLAS is one of the seven particle detector experiments constructed at the Large Hadron collider (LHC), a particle accelerator at CERN in Switzerland. The experiment is designed to take advantage of the unprecedented energy available at the LHC and investigate many different types of physics that might become detectable in the energetic collisions of the LHC, like the improved measurement of the Higgs boson, the possible clues for CP violation, the properties of the top quark, etc. In July2012, ATLAS is one of the two LHC experiments involved in the discovery of a particle consistent with Higgs boson, which is great news to the world. In order to extend and support the ATLAS physics reach, the ATLAS collaboration has devised a staged program in three phases. The Phase-I upgrades require ATLAS to keep the100kHz trigger bandwidth with increased luminosity and more severe "pileup". In this case, the development of new detector and readout components are needed, which is also the primary motivation of the Phase-I detector upgrades.Based on the design of front end electronics in ATLAS LAr calorimeter Phase-I upgrade, we discuss the following key points in this thesis. Firstly, we explore the feasibility of the LAr Trigger Digitizer Board (LTDB) and propose a "step-by-step" development plan. Then, we introduce key parts evaluation, and their test boards design as well (check both electronics function and radiation performance). Next, we detailed explain the design of quarter-slice LTDB prototype system and the set up of its test system. We also analyze the test results. In the last part, we briefly present the development of LTDB demonstrator and show its latest test result. This thesis is arranged as follows.In chapter1, we illustrate the importance of calorimeter applied in partical physics. First of all, we show different categories of the calorimeter and explain their application field. Also, we discussed the R&D of new types of calorimeter. Then we summarize the features and the trend of the calorimeter electronics. At last, we describe the structure of ATLAS LAr calorimeter and the requirement of its electronics design.In chapter2, we present the general background of ATLAS LAr calorimeter Phase-Ⅰ upgrade. Firstly, we explain the structure of LHC and ATLAS detector and show their upgrade plans up to2030and beyond. Then, we give physics requirements of the Phase-Ⅰ upgrade. Finally, we discuss the objectives of the Phase-Ⅰ LAr upgrade project and the compatibility with Phase-Ⅱ upgrade.In chapter3, we give an overview of the existing readout and trigger system. We show the granularity distribution of the calorimeter and the detector signal features at the beginning. Then, we briefly introduce the design parameters, general structure and sub-modules’function of the existing readout electronics system. At last, we discussed the limitations of the existion LAr electronics and give the upgrade objective of the current readout and trigger system.In Chapter4, we discuss the feasibility of different LTDB design schemes. Based on the Phase-Ⅰ upgrade background, we give the following features of the LTDB baseline design:Each LTDB will process up to320fine granularity "Super Cell" signals, includs sampling "SC" signals at40MHz, packaging digital "SC" signals and sending them to the back end digital processors via optical fiber. It also forms the legancy trigger signals (layer sum signals) and sends them to the TBB (Tower Builder Board) to keep the current analog chain unaffected. Then, we focus on the development of LTDB, which basically consists of the following aspects:the mechanical design, the power supply, the choice of form factor, the selection and evaluation of the key parts used on LTDB. In this chapter, it also makes a "step-by-step" implementation plan for LTDB.In chapter5, we present the quarter-slice LTDB prototype system. It consists of quarter-slice digital mother board (deal with80"SC" channels), analog mezzanine, optical mezzanine and analog injection board. Detailed description of the schematic design and PCB layout of each module is given in this chapter. Then, we discuss the test set up for the quarter-slice LTDB prototype system, and step-by-step evaluation test as well. At last, we show the test results of the quarter-slice LTDB prototype.In chapter6, we introduce the LTDB demonstrator system. It consists of full-size digital mother board (process320"SC" channels), analog mezzanine (v2.0), PPOD mezzanine cards (v2.0), QSFP mezzanine card and LTDB mechanical board. Finally, we briefly present the design of LTDB demonstrator system and show its latest test results.Finally, in chapter7, we conclude this thesis and summarize what have been achieved.