| During the past50years, Filed-Programmable Gate Arrays (FPGAs) have becomeone of the most popular implementation media for digital circuits. Compared withApplication Specific Integrated Circuits (ASICs), FPGAs allow designers to achievelower Non-Recurring Engineering (NRE) costs and short time to markets for theirdesigns. But scale, speed and power of the designs implemented in FPGA are limited,So, FPGA can compete with ASIC by using newly developed technology and increasingsize. While, these methods not only enhance the performance but also increase thedesign, manufacture and application challenge for FPGA. So, how to efficientlyimplement FPGAs, improve the manufacturability and change the design experiencebecomes a hot topic in industry and academic.In this paper, our researches mainly focus on the design, manufacturability anddesign tools. Through improving the Electronic Design Automation (EDA) algorithm,we optimized the FPGA implementation method and design tools. To verify ourimprovement, we involved the testbench analyzing method and modeling method. Wemade three innovations in this paper:1. For the problem of FPGA chip implementation, we cut down the time for FPGAlayout design. Classic FPGA layout design automation flow is based on the manuallydesigned building cells, and we automated their layout design, with the keyimprovement of the chaining algorithm for the small transistor group layout automation.2. For the manufacture problem of FPGA chip design, we improved the printabilityof FPGA chip by limiting the layout style which can also improve the process variationand Probability of Failure (PoF). Quantitative analysis shows that our new layout stylecan achieve33%variation improvement and21.2%PoF improvement with only9%area penalty, which could be potentially recovered by process window optimizationthanks to its superior printability.3. For the problem of FPGA design tool optimization, we changed designer’s usingexperience through speeding up the compiling time of FPGA design, which indeedoptimized the application cost. After analyzing compile tool chain, we found thecompiling time could be shrinked through the parallelization of the routing algorithm.We proposed a parallel routing algorithm based on geometric partition. The algorithmpartitions the routing region into several parts, and the nets which belong to differentparts can be routed concurrently because there is no data dependency between them. So,our parallelization method can achieve good speedup without compromising the qualityof routing result. |
