Design Of Non-binary Successive-Approximation-Register Analog-to-Digital Converter

As the bridge connecting analog world and digital system,the Analog-to-Digital Converters(ADC)are widely used in digital multimedia,communication,bioelectric,sensing and control.The performances of ADCs,such as sampling frequency,resolution and power consumption,directly determine the capabilities of the entire electrical system.As the process dimension keeps shrinking and power supply voltage keeps decreasing,the second order effects of devices are more and more significant and the design of analog circuits becomes a great challenge.Due to its simple structure with only one analog building block,which is comparator,the SuccessiveApproximation-Register Analog-to-Digital Converter(SAR ADC)is easier to be designed in nano-scale CMOS process than other kinds of ADCs and its power consumption is also much lower.However,due to the serial quantization mode,the speed of SAR ADC has always been slower than other ADCs,limiting its applications.On the other hand,the requirement on the matching of DAC capacitors becomes more and more critical with the increasing of ADC resolution,leading to large capacitor values.Therefore,the power and speed of high accuracy SAR ADC are sacrificed a lot.To solve these problems,the research of this thesis was focused on the following topics: the principle of non-binary coding,the DAC structure used for non-binary quantization,the design optimization of non-binary DAC,calibration techniques of capacitors mismatch,the design of asynchronous timing circuits and bandgap reference with self-calibration.The primary achievements and innovations of this thesis are described in detail as follows.1.Research on the architecture of non-binary SAR ADC: The conversion speed of traditional binary SAR ADC was firstly analyzed theoretically.The ADC sampling frequency is limited as the DAC needs long enough time to settle within 0.5LSB error for every bit cycling.In view of this problem,the non-binary quantization algorithm was analyzed.Redundancy can be introduced by decreasing the radix to a fractional value smaller than two.As a result,the input signal can be represented by two different non-binary codes,relaxing the requirement on the DAC settling accuracy.Non-binary quantization based on unit capacitors was then proposed to avoid the disadvantages caused by fractional value capacitors,such as poor matching,truncation error during the transcoding,unable to utilize split capacitor array etc.Based on these theories,two DAC structures suitable to be used in non-binary SAR ADC were proposed,which are VCM-based DAC and split-capacitor DAC.The DAC settling accuracy can be relaxed to half of the redundancy from 0.5LSB by setting the reference level generated by the DAC in the middle of the redundancy range.Finally,a DAC design optimization method was proposed to maximize the conversion speed by exploiting the redundancy.2.Research on calibration techniques of capacitor mismatch: The capacitor mismatch error must be calibrated if small capacitors are used for high resolution SAR ADC.Three different calibration techniques were proposed in this thesis,including the analog domain foreground calibration,the analog domain background calibration and the digital domain background calibration.The two analog domain calibration techniques are applied to binary SAR ADC.Their basic principle is to compensate the difference between the capacitor under calibration and the sum of all of its lower bits capacitors.For non-binary SAR ADC,a digital domain background calibration based on capacitor swapping was proposed.The termination capacitor in the DAC is taken as the reference capacitor and all other unit capacitors are calibrated with respect to it.Each input signal is quantized twice and the capacitor under calibration is swapped with the reference capacitor during the second conversion.According to the difference of two conversion results,the digital weight of the capacitor under calibration is updated by LMS algorithm.The calibration method with two reference capacitors was proposed to reduce the number of capacitors to be calibrated.3.The design and measurement of a bandgap reference with self-calibration: The bandgap circuit provides the ADC with a reference voltage insensitive to temperature and supply voltage,but the conventional bandgap suffers from a poor initial accuracy.To solve this problem,a bandgap reference with self-calibration was proposed in this thesis.After the circuit is power up,two different initial reference voltages can be obtained by swapping the relative positions of all the devices that need to be well matched.The final output voltage is equal to the average value of the two initial reference voltages through automatic trimming.This design results in the same effect of chopping technique,whereas the clock signal is not needed after the calibration is done and thus the voltage ripple is cleared up.Compared to bandgap with traditional trimming technique,this circuit is smarter as it does not need to be manually trimmed individually.The bandgap reference with self-calibration was fabricated on a 65 nm CMOS process.The measurement results show that the 3σ inaccuracy reduces from ±12.6 % to ±1.0 % after calibration.The temperature coefficient is 23.6 ppm/°C and the PSRR reaches 62.8 dB.4.The design and measurement of a non-binary SAR ADC: A 12 bit 5 MSPS non-binary SAR ADC was designed.To further improve the speed,asynchronous timing with self-timed control was utilized and an adaptive delay circuit was proposed,which automatically adjusts the bit cycling time according to the sampling frequency.A nonbinary VCM-based DAC with unit capacitors was designed.The total capacitance and area is reduced by exploiting split capacitor array.To improve the sampling linearity,the bootstrap switch was designed to sample the input signal.The comparator is a clocked latch with two stage pre-amplifiers to limit the noise.The digital circuits for calibration were synthesized with Verilog codes and they were integrated with the analog circuits on a single chip.The ADC was fabricated on a 65 nm CMOS process and the core area is 0.77 mm × 0.65 mm.The measurement results show that the ADC performance is improved significantly after calibration.The DNL and INL are 0.73 LSB and 1.24 LSB respectively and the SNDR and SFDR are 67.7 dB and 85.5 dB respectively.The ENOB reaches 11.0 bit and power consumption is approximately 6.87 mW.