Research Of Flip-flop Design And Its Power Control Technologies

With the continuous development of CMOS integrated circuits,human society is entering a new era of information.On one hand,the process dimension of the integrated circuit technology is shrinking,the number of transistors and the clock frequency are increasing dramatically,which make the power consumption problem more and more prominent.On the other hand,with the rapid development of the integrated circuit industry,cryptographic chips have entered all fields and also promoted them.Meanwhile,compared with the traditional cryptographic analysis,the power analysis can extract the secret information of cryptographic device by combining the algorithm design details and the power leakages.To sum up,power consumption conducts a very important role,which not only acts as a performance metric for synchronous digital circuit systems,but also serves as leakage information for side channel analysis(SCA),have a very important role.Therefore,the study of power control technologies has a crucial role for different areas of the chip designs.In the synchronous digital VLSI system,the clock system is mainly composed of the clock distribution network and sequential components,which account for about 30%-60%of the total power consumption of the system.The sequential components mainly contain flip-flops(FFs)and latches,which accounts for 90%of total clock system power.In addition,the FFs act as basic components of a cryptographic circuit,of which the power consumption is a major source of leakage information for SCA.Therefore,the study of FF-based power control technologies with corresponding applications on FF designs is quite important for different application environments.In view of above concerns,we first study the concept and composition of FF-based power control technologies,which includes low-power control technology,balanced power control technology and fluctuating power control technology.Then we have proposed a variety of innovative and high performance FFs based on the above techniques,and have carried on some related simulation experiments.First,in order to reduce the power consumption of FFs,we have investigated the applications of clock-gating technologies based on the reduction of the switching activities in the design of low power FFs.Therefore,we have proposed two novel kinds of clock-gating technologies,i.e.,clock triggering edge selecting-control technology and embedded clock-gating technology,which can significantly reduce the total power consumption by suppressing the redundant clock signals or the redundant edges of clock signals in the FF.Then we have designed four novel pulse-triggered flip-flops based on these two clock-gating technologies and the advantages of binary and ternary pulsed flip-flops:Dual-edge explicit pulse-triggered FF based on clock triggering edge control technology(DEPFF-CEC);Implicit pulsed-triggered FF with embedded clock-gating and pull-up control scheme(IPFF-CGPC);Dual-edge implicit pulse-triggered FF with embedded clock-gating scheme(DIFF-CGS);Ternary D-type FF based on embedded clock-gating scheme(CG-TDFF).The above four FF designs not only share the some similarities,but also have their own focus.The similarities lie in that they all have employed the clock-gating techniques and have outstanding low power consumption characteristics,especially when the switching activities are low.For example,IPFF-CGPC provides 58.90%-85.89%reduction in total power dissipation compared with its counterparts.Usually the data activity factor of typical CMOS logic is in the range of 0.08-0.12,whereas the clock activity factor is 100%.Therefore,the four proposed low power FFs are especially suitable for low power circuit designs and standard-cell library designs.Meanwhile,the four FFs have their own focus.In specific,DEPFF-CEC is a dual-edge explicit pulse-triggered FF,which has separate clock pulse generator and has the advantage of soft clock edge;IPFF-CGPC and IPFF-ECGPC are implicit pulsed-triggered FFs.IPFF-CGPC exhibits extremely outstanding low power characteristic even when the switching activity is high.IPFF-ECGPC has no threshold voltage degradation problem,which is robust against process variations.DIFF-CGS is a dual-edge implicit pulse-triggered FF,which has made better use of available clock edges.CG-TDFF is a ternary D-type FF,which has all the advantages of ternary circuits,such as smaller area,shorter signal wire,more clock triggering edges,etc.Second,in order to improve the resistance of the circuits against power analysis,we have investigated the cell-level balanced-power based SCA countermeasure technologies with their applications in designing FFs.So we have proposed a novel full-custom FF design(DyCML-FF)based on dynamic current mode logic,which has a 'constant power consumption and is independent of the input data.According to the simulated comparison results with the sense-amplifier based logic-based FF(SABL-FF)and the wave dynamic differential logic-based flip-flop(WDDL-FF),it is obvious that the normalized energy deviation(NED)and normalized standard deviation(NSD)performance of DyCML-FF has improved significantly,which proves its improved SCA-resistance.In addition,DyCML-FF has a minimum PDP due to its low power efficiency and high speed performance,which is 10.60%and 88.35%smaller than SABL-FF and WDDL-FF,respectively.Therefore,the DyCML-FF proposed in this paper is a suitable choice for sequential components in ASICs where security and PDP are strictly required.Finally,in order to further improve the resistance of the circuits against power analysis,we have firstly proposed a novel cell-level SCA countermeasure technology—fluctuating power logic(FPL),and then applied it on FF designs,which leads to a novel FF based on fluctuating power control technology.The employment of cascaded voltage logic(CVL)distorts the relationship between actual power consumption of FF and the fixed data transition,thus shaking the cornerstone of SCAs.And with the help of compensation unit(CU),the DPA resistance of the FPL-based FF designs can be greatly enhanced.The SCA-resistance of the proposed scheme is illustrated by FF-based simulation.HSPICE based simulation results show that the modified flip-flop is resistant against power analysis at the cost of doubled power dissipation.Two illustrative case studies of PRESENT and AES substitutions,which are based on standard-cell logic(SC),wave dynamic differential logic(WDDL)and FPL logic,have been explored as a preliminary step of real attack scenarios.The resistance of FPL-based circuits against SCA is evaluated by the correlation power analysis(CPA)and the test vector leakage assessment(TVLA).Furthermore,our proposal can be combined with other cell-level SCA-resistant logics to overcome the defects of the unbalanced complementary output capacitive loads.The proposed FPL logic outperforms other counterparts in consideration of both security and cost,which renders it as a practical solution in resource-constrained systems.