Low Power Flip-flop Design And Optimization Based On 28nm Process

With the rapid development of Very Large Scale Integration Circuit (VLSI) design, and semiconductor technology constantly updated, make the performance of chip has been greatly improved, a growing number of smart mobile devices, smart wearable devices emerge on the market. The constant improvement of the chip integration, make the chip power consumption and power consumption of the density problem is becoming more and more prominent. The power consumption increase will cause the chip temperature increase, seriously affecting the reliability of the circuit. For mobile smart devices, the power consumption increase will reduce its battery life. Low-power design has become an important research direction of VLSI design. In all the energy of a chip, the power consumption of the clock network accounted for 30%-50% of the total power consumption, and the flip-flop occupies the main part of the clock network. Therefore, the design of low-power flip-flop has important significance to reduce the overall power consumption of the circuit.This paper analyzes the power consumption of CMOS circuit source, and some performance parameters of flip-flop, and practical example a typical master-slave flip-flop, introduces some theoretical knowledge about the flip-flop. In the low-power design, add the clock gating circuit is a common design method, the principle of clock gating technology is the use of enabling signal control circuit in particular clock cycle let it idle, and make the circuit in need of work is activated, clock gating technology application reduced the overall power consumption of the circuit. This paper design a low-power flip-flop based on the clock gating technology, it can well reduce the dynamic power consumption due to the signal turn. In a certain clock cycle, if the input signal is equal to the output signal, i.e. the input signal remain unchanged, then, the gating clock signal can control the flip-flop in the idle state. Finally, based on the 28nm process for functional simulation, compare and analyze the performance of several flip-flops. Analysis available, the new design of the flip-flop on reducing power consumption has a good effect.Secondly, use logical effort method to optimization some existing master-slave flip-flops and the new design of the double clock gating flip-flop. The logical effort method does not depend on parasitic parameters, so that the design of circuit can by a simple calculation to obtain a minimum delay in the early stage have a reliable assessment. Flip-flop optimized by logical effort method to reach the fastest speed in theory, designer can apply it in the critical path of high speed circuit according to its characteristic.