Design And Implementation Of Ultra Low Power 16 Bit Successive Approximation Analog To Digital Converters

One of the most important components in modern electronic system is analog-to-digital convertor（ADC）,which is the bridge between the real word with the continuous time analog signal and the digital signal process system with the discrete time digital.The signal can be processed by digital signal process system efficiently.Recently,with rapid development of the communication technology,cloud computing,big data and medical electronics,the demands for ADCs are increasing urgently.At the same time,the requirements on ADCs are getting higher and higher.In short,high performance,low power and low-cost ADCs are the aims and difficulties of integrated circuit design.This thesis discusses the research on the successive-approximation-register（SAR）ADC and the critical building blocks:the capacitive digital-to-analog convertor（CDAC）mismatch calibration,the optimization of SAR logic delay and the design of low noise comparator.A novel foreground digital calibration method for the CDAC mismatch is proposed.A SAR ADC prototype is designed and implemented to show the effectiveness of the proposed calibration method and the proposed low power techniques.The main contributions of this thesis are briefly stated below:The existing CDAC mismatch calibration methods are analyzed and summarized.Then,a foreground digital CDAC mismatch calibration method is proposed.It uses the redundant capacitor and the lower bit capacitor to measure the error voltage corresponding to a certain capacitor.And these error voltages are utilized to obtain the right weight of each capacitor.The proposed calibration method needs no extra CDAC and can obtain a high-resolution SAR ADC.Noise and power are serious problem for high resolution SAR ADC.This thesis adopts Floating Capacitor CDAC technique,allowing a large input range under a low core supply voltage.Thus,the noise margin is increased and the total power of ADC is decreased.The total ADC power can be reduced by 34.2%in this case.This thesis proposed a modified Split Floating Capacitor CDAC,which avoids the large offset in the traditional Floating Capacitor CDAC.Split-capacitor CDAC still needs a common mode voltage,which is generated by a buffer or other way.Either of them needs extra power,especially for high resolution SAR ADC.This thesis proposed a V_cm-free CDAC technique,which utilizes Split-capacitor CDAC and power supply voltage to obtain common voltage.Thus,common mode voltage generator can be omitted,which reduces the total power by 6%.This technique can be used in the Split Floating Capacitor CDAC architecture.It can be shown that there exists gain error and offset error.For the proposed CDAC mismatch calibration method,some modifications need to be done to the calibration method.To reduce the delay of SAR logic,open-windowing SAR logic is also discussed in this thesis.However,open-windowing SAR logic has the problem of error due to offset of latch.This thesis proposed an open-windowing SAR logic that avoid this error.Besides,the noise,offset and power of comparator for high-resolution SAR ADC are analyzed.It is shown that to reduce the noise,the decreasing the bandwidth of comparator is equivalent to increasing the first input stage transconductance of comparator.A 16 bit 1MS/s SAR ADC prototype is implemented in a 0.18μm CMOS technology.The chip area is about 1.58 mm×1.6 mm including digital logic and pads.It consumes totally6.75 mA from a supply voltage of 1.8 V and 3 V.The measurement results show the DNL and INL are-0.86/+0.97 LSB and-1.74/+2.46 LSB,respectively.For full swing with 10 kHz input signal,the SFDR and SNDR are 94.33 dB and 86.16 dB,respectively.The FoM_S and FoM_W are 164.9 dB and 0.41 pJ/conv.-step,respectively.The testing results show that this chip achieves competitive performance from the comparison with the state-of-art high resolution SAR ADC.