Impact of size effects and anomalous skin effect on metallic wires as GSI interconnects

The 2006 International Technology Roadmap for Semiconductors projects that for 2020, interconnects will be as narrow as 14 nm. For a wire with such dimensions, the collision rate of electrons with the surfaces will be a significant fraction of the total number of collisions, causing an increase in the total resistance of the wire. At the same time, interconnections operate at higher frequencies, such that electrons are confined to a sheet near the surface; therefore, the effective cross-sectional area of the conductor decreases and the effective resistance increases. For a wire that operates at ultra-high frequencies, such that skin depth and the mean free path of the electrons are in the same order, skin effect and surface scattering should be considered simultaneously. This is known as the anomalous skin effect (ASE).;The objective of this work is to identify the challenges and opportunities for using GSI interconnects in the nanometer and GHz regime. The increase in the resistivity of a thin wire caused by the ASE is studied. The delay of a digital transmission line resulting from this effect is modeled. Compact models are presented for the bit-rate limit of transmission lines using a general form of resistance that for the first time simultaneously considers dc resistance, skin effect, and surface scattering. A conventional low-loss approximation that is only valid for fast rising signals is also relaxed. In contrast to previous models, it is shown that the bit-rate limit of a transmission line is not scale-invariant. It is also shown that the error of previous models is large (e.g. 80% for bit-rate limit equals reciprocal time-of-flight) if the bit-rate limit is not considerably larger than the reciprocal time-of-flight.;The impact of surface and grain boundary scatterings on the design of multi-level interconnect networks and their latency distribution is studied. For high-performance chips at the 18 nm technology node, it is shown that despite a more than four times increase in the resistivity of copper for minimum-size interconnects, the increase in the number of metal levels is negligible (less than 7%), and interconnects that will be affected most are so short that their impact on chip performance is inconsequential. It is shown that for low-cost applications where very few wiring pitches are normally used, the number of metal levels needed to compensate for the impact of size effects on the average rc delay of a copper interconnect is drastically high. For a case study chip implemented at 14 nm with an interconnect network with two-tiers, it is shown that a 60% increase in the number of metal levels is needed to address a five times increase in the resistivity of minimum-size wires.;As technology advances, it becomes more and more challenging to design on-chip power distribution networks. An optimization methodology has been presented for power distribution interconnects at the local level. For a given IR drop budget, compact models are presented for the optimal widths of power and ground lines in the first two metal levels for which the total metal area used for power distribution is minimized. Wire widths and thicknesses at the end of the 2006 ITRS are projected to scale down to 14 nm, and size effects are expected to increase copper resistivity by more than four times. Either a three times increase in wiring area for local power lines or a two times decrease in the power via pitch is necessary to compensate for size effects. However, decreasing the power via pitch will increase the power via blockage factor for all metal levels between Metal 2 and the top-most levels with global power grids. The results shows that for 2020, the optimal design that minimizes both the area needed for the local power distribution and power via blockage factor, occurs when power via pitches in the x and y directions are equal and widths of the power lines in Metal 1 are three times the minimum size wires in Metal 1.