Low power and reliability assessment techniques for advanced processor design

The rapid scaling of silicon technologies over the past decade has introduced some strenuous constraints for processor design. The technology progression has exacerbated the power problem which has further increased the necessity to consider design reliability. Static power dissipation that used to be negligible in past is expected to be a major component of overall processor dissipation. In this research, we present techniques that reduce both static and dynamic power dissipation in modern processors while not compromising the processor reliability as whole. We also present a tool BDEC that can be used to compare the reliability of different possible implementations of major processor functional units to choose more reliable implementations in future processor designs.;The proposed techniques reduce both static and dynamic power dissipation in modern processor designs. While dealing with low power design one important design aspect is that the low power technique must not be power hungry itself. The beauty of the presented low power techniques is that they do not have huge hardware implementation cost, rather they use existing hardware to control power dissipation. Power dissipation overhead of presented techniques is minimal.;Smaller and smaller feature sizes and increased power density of modern processors which has resulted in high chip temperatures has increased the importance of reliability consideration in processor design. Since in future we will need to build reliable systems using unreliable components modern processor design will need to be geared towards considering design reliability during the early phases of the design. To help compare various design alternatives we developed a tool: BDEC which gives the reliability of a combinational circuit in terms of gate error probabilities and input error probabilities on the primary inputs.