| This dissertation develops a methodology, called ABVFI, which addresses effects on design dependability from today's integrated circuit (IC) manufacturing techniques. While, technology scaling is opening up new possibilities in the design of ICs to meet the demands of today's processing needs, as manufacturing technologies advance to smaller transistor sizes, hardware components become more and more susceptible to single event upsets and other types of failures.;ABVFI allows fault injection to be performed at the register transfer level of a design, and extends an emerging technique called assertion based verification, a variant of model checking, to mathematically analyze design behavior in the presence of faults. Given a defined set of fault models and input space, this method considers all possible combinations of faults across both time (when the fault occurs) and space (where the fault occurs), for a complete analysis of fault coverage.;The use of ABVFI provides benefits to both safety-critical designs and commercial information technology systems. For safety-critical systems, stringent dependability requirements necessitate rigorous safety analyses. Furthermore, strong safety arguments are required for design certification. ABVFI provides this through the underlying model checking technique, which is both thorough and repeatable.;The development of commercial systems is primarily concerned with making trade offs among various design constraints (e.g. area, power, performance, etc.), such that in the end a near optimum design solution is obtained. ABVFI provides an efficient and accurate fault coverage analysis tool that can be used by designers to make well educated design decisions based on dependability requirements. |
