Ultrahigh speed indium gallium arsenide/indium phosphide DHBT devices and circuits

This work examines the efforts pursued through vertical and lateral scaling to increase the bandwidth of InP based DHBTs. Through process development, device performance has improved from lateral scaling and reduced contact resistances. A high-yield 0.5 mum narrow mesa emitter junction technology has been realized. The contact resistivity rhoc for the emitter, base, and collector layers has been reduced to less than 10 O · mum 2, a 2:1 improvement. With this base-contact rhoc and a typical base sheet rhos ≅ 600 O/□, the metal-semiconductor transfer length Lt has been reduced to 120 nm, and 0.3 mum base contacts have been realized. This has substantially reduced the extrinsic Ccb with minimal increase to the base resistance Rbb.; The reductions to the extrinsic capacitive and resistive parasitics allow the active collector thickness Tc to be thinned for increased device bandwidth. To achieve minimum Ccb/I c ratio as Tc is reduced, the maximum current density will increase Je = J Kirk ∝ T-2c . The power density will similarly increase P = Ic · Vce = JeAe · Vce. Improved device heat-sinking to the high thermally-conductive InP substrate for reduced HBT thermal resistance thetaJA (K · mum2/mW) must be considered during HBT design to prevent excessive device self-heating as the operating power density increases. For the device improvements discussed, the follow results have ensued from each collector scaling generation: Tc=210 nm→ft/fmax=276/451 GHz,Tc=15 0nm→ft/f max=391/505GHz, Tc=120 nm→ft/fmax=450/490 GHz,Tc=10 0nm→ft/f max=491/415GHz.; Static frequency dividers were designed and fabricated utilizing an HBT with a collector thickness of 150 nm. The amount of DeltaV logic consumed by the parasitic emitter resistance was the scaling limit for these circuits. A dense wiring scheme is utilized to reduce interconnect delays, and the signal integrity was maintained through the use of a low-epsilonr, thin-film microstrip environment. Divide-by-2 designs fabricated at GCS and UCSB had a maximum toggle rate of fclk,max = 153 GHz and 142 GHz, respectively.