| As the first free-standing 2D crystal, graphene was discovered in 2004 by Andre Geim and Kostya Novoselov of Manchester University using a technique called micromechanical cleavage [1]. Since then, graphene has attracted vast interest in solid-state physics, materials science, nanoelectronics and bioscience. Graphene is considered as a promising electronic material in post-silicon electronics due to its potential compatibility with planar technology while maintaining much of the transport advantages of carbon nanotubes (CNTs). Graphene transistors have behave high intrinsic carrier mobility (>10,000 cm 2/V•s) [2], large saturation velocity (5.5x107 cm/s)[3], and high on-state current density (>3 A/mm)[4, 5],which makes it tobe a promising candidate for high-frequency devices. Graphene-based field-effect transistors (FETs) with a cutoff frequency of 300 GHz[5] has been achieved on exfoliated graphene. For top gate graphene FETs, J. S. Moon et al. reported epitaxial graphene FETs on SiC with a mobility of 6,000 cm2/V•s[4]; Xuesong Li et al. reported extracted mobility of 4,050 cm2/V•s with CVD graphene on Cu[6]; Lei Liao et al. reported extracted mobility of 23,600 cm2/V•s with mechanical exfoliated graphene[7].;However, mass production of high quality graphene on insulator substrate is a bottleneck for the practical application of graphene as an electronic material. Mechanical exfoliation and wet chemistry-based approaches cannot increase to large-scale and well-ordered graphene. SiC epitaxial has the prospect of producing graphene over an entire wafer, but it requires expensive substrate. For CVD graphene on metals, PDMS or PMMA transfer is typically used, resulting in contamination between graphene and the new substrate, ultimately degrading mobility. For high frequency application of graphene FETs, low parasitic capacitance, small series resistance and high mobility are essential elements. Most of the graphene FETs with self-aligned structure published to date [5, 8, 9] are with top gate structure. For the top gated graphene FETs, the gate and source/drain are on the same side of graphene, which may cause large fringing capacitance especially for short channel devices. Also the way to make the source/drain self-aligned will restrict the contact metal thickness to around 10nm, which will address the reliability issue of the contact.;With the goal of overcoming these difficulties, this project investigates an approach to mass product high quality graphene and corresponding transistors fabrication. Ni dots with single or few grains were achieved by annealing. Single layer graphene with good crystalline quality has been grown on Ni dots. The patterned graphene films were transferred to insulating substrates by wafer bonding and etch back technique, which gives zero mis-alignment, low contamination as well as high yield(>90%). Graphene based field-effect transistors with self-aligned buried gate were fabricated with this method. The field effective mobility of 6,100 cm2/V•s and 24,000 cm 2/V•s was achieved before and after subtraction of contact resistance, respectively. The extracted source/drain contact resistivity between Ti/Pd/Au and graphene was found to be in the order of 10-7 O cm 2. The channel length was scaled down to 100 run, high transconductance (438mS/mm) was maintained in 100nm channel length devices. These results demonstrate the potential of this method as a candidate for mass production of graphene transistors for RF application. |
