Thermal management of three-dimensional integrated circuits using inter-layer liquid cooling

Heat removal technologies are among the most critical needs for three-dimensional (3D) stacking of high-performance chips. This research reports a 3D integration platform that can support the heat removal requirements for 3D integrated circuits containing high-performance microprocessors.;This work shows the use of wafer-level batch fabrication to develop advanced electrical and fluidic three-dimensional interconnect networks in a 3D stack. Fabrication results are shown for the integration of microchannels and electrical through-silicon vias (TSVs). A compact physical model is developed to determine the design trade-offs for microchannel heat sink and electrical TSV integration. An experimental thermal test-bed for evaluating a 3D inter-layer liquid cooling platform is developed. Experimental thermal testing results for an air-cooled chip and a liquid-cooled chip are compared. Microchannel heat sink cooling shows a significant junction temperature and heat sink thermal resistance reduction compared to air-cooling. The on-chip integrated microchannel heat sink, which has a thermal resistance of 0.229 °C/W, enables cooling of >100W/cm2 per tier, while maintaining an average junction temperature of less than 50°C. Cooling liquid is circulated through the 3D stack (two layers) at flow rates of up to 100 ml/min.;The ability to assemble chips with integrated electrical I/Os (density of ∼1600/cm2) and fluidic I/Os at each strata interface is demonstrated using various assembly and fluidic sealing techniques.