Properties of misfit dislocations in thick silicon epitaxy

The focus of this dissertation is a rigorous examination of the plastic strain relaxation in p/p+ silicon wafers. Due to the very low lattice mismatch employed (∼0.016%), a thick epitaxial layer on the order of several μm can be grown via high temperature chemical vapor deposition without the onset of lattice relaxation. At the relaxation onset, sparse, long interfacial misfit dislocations nucleate only around the wafer edges and, in a few cases, at the laser mark. The possibility to conserve the elastically strained epilayer via careful control of mechanical defects around the wafer edges was investigated. The special relaxation characteristics in high quality p/p+ silicon allow study of the basic properties of single defect segments using non-destructive x-ray topography. Defects caused by thermal gradients in the wafer during the epitaxial processing were identified. The detrimental effect of misfit dislocations on devices grown in relaxed epilayers was studied.; The main conclusions of the dissertation are as follows: (A) A careful combination of edge treatments, including edge damage removal steps before epitaxial layer application, helps significantly reduce misfit dislocations in p/p+ wafers. The type of backside seal on the p+ substrate wafers influences the edge nucleation characteristics. (B) The expected extension of pre-existing misfit dislocations during further processing for MOS devices was quantified. The glide activation energy was determined to be ∼1.94 ± 0.1 eV. (C) The interaction of single misfit dislocation segments was studied during post-growth annealing cycles. Misfit dislocation cross-slip was frequently observed. Due to the round geometry of a wafer, a variation of tilt can be expected from preferential cross-slip. Explanations are given for observations in highly mismatched systems. (D) The influence of a high point defect concentration on misfit dislocation nucleation and glide was studied using silicon self-ion implantation. Retardation of layer relaxation was observed. (E) Thermal slip was shown to occur during epitaxy of thin lattice-matched wafers. A roughening effect on the wafer surface was found. (F) A detrimental consequence of the threading ends of misfit dislocations on electrical properties of devices grown in the epilayer was determined.