| As CMOS technologies enter the sub-100nm realm, Integrated Circuit (IC) designers are challenged to create reliable, low-power chips that can help extend product battery and overall lifetimes. These challenges are exacerbated by technology scaling, with which comes increasing transistor leakage current, parameter variations, and generally less reliable on-chip components. As such, there stands a great need in the chip-design community to decrease IC power, and do so without damaging the overall circuit reliability.;This work examines a particular subset of VLSI systems, both CMOS and nano-electronic based, with aims to help reduce on-chip power, and improve the overall robustness of such circuits. The array of chosen circuits represents a subset of the standard, state-of-the-art structures found in today's IC designs. These circuits include traditional Static Random-Access-Memories (SRAM), multi-core processors, and non-volatile nano-electronic resistive memories.;Specifically, this dissertation presents four unique projects. The first project combines a circuit design technique with a data encoding method to help increase the allowable memory bank size of ultra-dense, nonvolatile memories, such as MRAM, phase-change memory, and molecular memory. The second project develops a sensor to track on-chip aging, particularly from sources like Negative-Bias Temperature-Instability. This sensor is designed to be embedded within the critical paths of modern microprocessors, and results highlight the functionality, accuracy, and overall sensor effectiveness. The last two projects examine a novel low-power design methodology, whereby individual circuit blocks and cores are "stacked" to reduce voltage across each element. The results from this project show that stacking applied to SRAM can reduce power by upwards of 93%. Furthermore, this methodology is applied to entire processor core designs, particularly targeting subthreshold voltages, whereby the technique is able to improve overall design efficiency. |
