Energy recovery techniques for CMOS microprocessor design

Power dissipation is an important aspect of digital computing systems because of battery life for portables and heat removal for high-performance systems. Energy-recovery CMOS is a new approach to low-power computing. The central idea is to recover and reuse circuit energies that would otherwise be dissipated as heat. It is a complementary approach to the well-known, conventional approaches of lowering the supply voltage and minimizing the switching capacitance.; This Dissertation is an investigation into energy recovery for low-power CMOS microprocessors. First, the relationship between energy recovery and reversible computing is explored. Computation models based on energy recovery are developed. CMOS circuits based on these models are straightforward to implement. Second, clock-powered logic is proposed as an energy-recovery CMOS approach which offers high energy efficiency with good performance.; The premise to clock-powered logic is that "all data are not created equal." Circuit nodes are classified by how much they contribute to the total dissipation. For CMOS, the classification is by the capacitance of the nodes. High-capacitance nodes are clock-powered and low-capacitance nodes are conventionally (e.g., dc) powered.; Energy is recovered from the clock-powered nodes. A methodology for designing clock-powered microsystems is developed that spans the basic circuit level to the system level. This methodology was tested on AC-1, a clock-powered microprocessor. AC-1 was analyzed both statically and dynamically. Static analysis included capacitance classification for AC-1 circuits nodes. Dynamic analysis included laboratory measurements with a power profile of the dc- and clock-powered nodes.; AC-1 was designed to operate in either an energy-recovery or conventional mode. When energy recovery was turned off, the 10% clock-powered nodes of AC-1 accounted for 90% of the dissipation. With energy recovery enabled, a five-fold power dissipation reduction was observed. AC-1 was also compared with a conventional, equivalent static CMOS implementation through device-level simulations. The results of these simulations indicated a two-fold power dissipation reduction advantage for AC-1.