| A strong demand for high-performance and high-functionality devices is driving the growth of flip-chip packaging, especially the flip-chip-on-laminate (FCOL) configuration. The present FCOL assembly process, with capillary-flow underfill, includes non-traditional manufacturing steps such as underfill dispense and cure. These processing steps can be time consuming and costly, making FCOL unfavorable for low-cost, high-volume assembly manufacturing. A number of different solutions to solve this problem have been proposed so far. These proposed techniques include use of fast-flow and snap-cure underfills, no-flow fluxing underfills, and wafer-applied underfill. FCOL assembly process with no-flow underfills and wafer-applied underfills have been discussed in detail here.; Assembly process with no-flow, fluxing underfills was studied, and reliability analysis was performed. Different fluxing underfill formulations were evaluated. Effect of die placement parameters, underfill volume and reflow profile on assembly yield was investigated. It was concluded that among all the process parameters, only the nature of reflow profile strongly affected the interconnect yield. Results of the environmental reliability tests indicated a relatively lower solder joint reliability with fluxing underfills, as compared to that with the traditional capillary-flow underfills. This was observed to be due to the material shortcomings such as low Tg (90°C) and high CTE (74 ppm/°C) of the present underfill system.; Although the use of fluxing underfills eliminates long capillary flow time and post-reflow cure, a dispense step is still required. A wafer-applied underfill process can potentially eliminate underfill dispense and cure steps, making FCOL truly transparent to the electronics assembly. For the implementation of wafer-applied underfill, it is necessary to develop a suitable wafer coating process and a compatible assembly process. A number of wafer coating processes such as spin coating, screen printing and stencil printing were evaluated. A three-step wafer coating process consisting of stencil printing and screen printing has been proposed. Key material properties such as rheology, B-staging characteristics and reflow sensitivity of the wafer-applied underfill materials were defined. A low-cost wafer bumping process, compatible with wafer-level underfilling process, was designed for fabrication of test wafers. A number of test wafers were coated and dies pre-coated with fluxing underfill and stress-relief underfill were assembled onto the boards. A 100% interconnect yield was observed in case of dies coated with fluxing underfill on bumps. Dies coated with fluxing underfill and stress-relief underfill layer showed low interconnect yield, mainly due to the non-collapsible nature of the present stress-relief underfill material. |
