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New process development for flip chip assembly

Posted on:2003-04-02Degree:Ph.DType:Dissertation
University:Auburn UniversityCandidate:Zhao, RenzheFull Text:PDF
GTID:1468390011981302Subject:Engineering
Abstract/Summary:
Flip chip on laminate (FCOL) provides the advantages of reduced product size and weight, improved electrical performance and higher input/output (I/O) counts over other assembly technologies. However, the industry has been slow in adopting FCOL technology because the conventional flip chip process is not transparent to high throughput surface mount technology (SMT). One issue often cited is the equipment and time associated with capillary underfill dispense, flow and cure. Several new techniques have been proposed as alternatives, such as fast flow, snap cure underfill; no-flow, fluxing underfill; and wafer level applied underfill processes. The fluxing underfill process and wafer level applied underfill process are investigated in this dissertation.; Experiments supplemented with mathematical models were conducted to characterize these new processes. Experimental methods represent the direct approach, while simulation allows one to examine the sensitivity of the process to a wide range of variables, some of which may be difficult to vary experimentally.; Surface Evolver-based models were created to calculate forces associated with solder joints and underfill fillet, chip stand-off, tendency to float, and solder joint and fillet geometries. For the fluxing underfill process, experimental results were compared to the model predictions. The coating thickness was calculated and used in the coating process development for the wafer-applied underfill process. The related component design issues were also addressed by the means of force calculation.; A number of fluxing underfills were examined to assess their performance in the assembly process. Predictive software was used to define the reflow profile for a complex PWB with a wide range of component sizes and thermal masses. The placement process was optimized through a design of experiments. With optimization, void-free assembly was achieved and the solder showed excellent wetting onto the bonding pads. Reliability tests were performed and the failure modes were identified to provide feedback to develop new underfills.; To utilize the wafer-applied underfills, an assembly process was developed to assemble the coated die onto the test board. Attributes of the materials and the coating were evaluated to provide feedback to improve the underfill properties and coating process quality. The influence of the material properties and the coating methods on the assembly process was assessed. Several critical issues, such as vision recognition of coated dies, placement tack, and reflow profile, were addressed.
Keywords/Search Tags:Process, Chip, Assembly, New, Underfill
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