Nonlinear stress analysis of electronic packages

To ensure good performance of electronic packages and assemblies, the material behaviors in a package or assembly have to be investigated during both the assembling and the operating stage. The material behavior can be studied using experimental approaches, which are time consuming and expensive. Compared to experimental approaches, computer models cost less. The rapid advances in packaging analysis capabilities enable researchers to analyze and solve complex problems using a number of available general-purpose computer programs. In the current work, the in-house finite element model, UASTRESS, is developed for this purpose. The UASTRESS is applied to compute the critical stress in two diamond-based assemblies and a SLIM/SHOCC package.; In this work, nonlinear finite element analysis is used to compute the critical stresses in two packages named ringframe and leadframe. Results confirm the experimental observation that the ringframe cracks during assembly. The leadframe package is numerically predicted to survive, in agreement with experiments, only if the plastic effect of Nickel is considered in addition to the plastic and creep effect of Cusil. The effects of considering elastic, elasto-plastic and elasto-plastic and creep on maximum stresses are compared in the two packages.; For the SLIM/SHOCC package, in the construction of flip chip BGAs on Multichip Modules (MCMs), the difference in coefficient of thermal expansion (CTE) between silicon chip, the BGA on MCM substrate, and the underlying FR4 motherboard is a significant factor in overall reliability. With flip chip underfill, the chip-to-substrate interface is strengthened significantly, resulting in less of a need for a substrate with a CTE match to silicon. Indeed, with the advent of CSP-like solder ball pitches of 0.5mm, the substrate-to-board interface can become critical if there is a significant CTE-mismatch between substrate and board.; Both the Single Level Integrated Module (SLIM) (Georgia Tech Packaging Research Center), being developed by the Georgia Tech Packaging Research Center (PRC) and Seamless High off-Chip Connectivity (SHOCC) (Dibbs et al., 1997), developed by an industrial consortium including the University of Arkansas High Density Electronic Center (HiDEC), incorporate a chip/substrate/board hierarchy with flip chips and solder ball BGA attachment.; In the present work, the resulting structure is considered for thermal stress analysis using finite element methods. The objective is to choose optimum materials in the 2nd and 3rd layer from the top so that the package survives due to thermal stresses. Three-dimensional linear elastic and viscoplastic analysis is done to investigate reliability.