Built-in self-test technique for high-speed phase-locked loops

Analog and mixed-signal testing is becoming an important issue that affects both the time-to-market and product cost of many modern electronic systems. An alternative approach to the success of products with these properties is Built-In Self-Test (BIST) of circuits and systems. A method which requires no external calibration or trimming is highly desirable since it could be used to speed up test time in the factory. The inclusion of BIST capabilities at the chip level will reduce the requirement for high-performance test equipment at every stage in the manufacturing process: chip, board, system, and field service.; This dissertation investigates a new structural testing of PLL using charge-based frequency measurement BIST (CF-BIST) technique. The technique uses the existing charge-pump as the stimulus generator and the VCO/divide-by-N as the measuring device to reduce the area overhead. Experimental results using National Semiconductor Corp.'s 0.25μm CMOS 900MHz PLL demonstrates low-cost and practical BIST solution. The area overhead is minimized by using the existing PLL circuitry for BIST structure. The test time is typically 12μsec, significantly faster than conventional testing.