Improving processor performance and simulation methodology

Although current processors are capable of executing multiple instructions per cycle, processor resources such as issue slots and functional units are frequently idle. Consequently, the processor's actual performance is often far below its theoretical maximum performance. To improve the processor's performance, this dissertation proposes two microarchitectural techniques that dynamically remove redundant and trivial computations. A redundant computation is a computation that the processor performs repeatedly while a trivial computation is one where the output is zero, one, 0xffffffff, or a shifted version of one of the inputs.; The first technique, Instruction Precomputation, compares each instruction's opcode and input operands against the opcode and input operands that are stored in the Precomputation Table. If there is a match, the Precomputation Table forwards the result for that redundant computation to the associated instruction. Using Instruction Precomputation yields an average speedup of 10.53% when using a 2048-entry Precomputation Table.; The second technique, the Simplification and Elimination of Trivial Computations, checks the opcode and input operands of each instruction to determine whether or not that computation is trivial or not. When the trivial computation can be simplified, the instruction is converted to another type of instruction that produces the same result, but with a lower execution frequency. When the trivial computation can be eliminated, the trivial computation hardware “computes” its result and removes the instruction from the pipeline. Dynamically simplifying and eliminating trivial computations yields an average speedup of 8.86% for the SPEC 2000 benchmarks and 4.00%, for the MediaBench benchmarks.; Due to cost, time, and flexibility constraints, simulators are used in the design of next-generation processors and to evaluate the performance of processor enhancements. Despite this dependence on simulators, computer architects usually approach the simulation process in an ad-hoc manner. Using statistically-based simulation methodology helps the architect decrease the number of errors in the simulation process, gives more insight into the effect of a processor enhancement, and provides statistical support to the observed behavior. This dissertation demonstrates the efficacy of using a Plackett and Burman design to improve how processor parameter values and benchmarks are chosen, and how processor enhancements are analyzed.