The Research And Design Of High Performance BWDSP Processor Instruction Cache

Digital signal processing technology is widely used in radar, electronic warfare,communication, sonar, voice and video etc. With rapid development of these various devices andtechnologies, the market puts forward higher requirements for the precision and speed of theintensive digital signal processing operation. Currently, there are dedicated ASIC device,general-purpose programmable logic devices (FPGA) and DSP processors which are used indigital signal processing devices. Among them, because of its flexibility limitations, the dedicatedASIC device has been unable to meet the demand of market and application. And making the useof general-purpose programmable logic device (FPGA) and DSP processor digital signalprocessing platform technology become mature with the rapid development of integrated circuittechnology and computer technology.In recent years, with development of intensive digital signal processing technology as well asthe complex conditions of function mode of modern electronic system, the market raises newrequirements for digital signal processing system which is based on digital signal processor, suchas capability of dealing with vector signal and wide bandwidth (signal processing bandwidthincreasing ceaselessly) signal, with a large dynamic range of gain and real-time variablebandwidth. High performance digital signal processor has become an important measure ofimproving digital signal processing system performance and reliability. The dynamic range of thegeneral DSP processor is relatively large, and it has high precision, data processing ability throughthe programming method to achieve the specific algorithm. During nearly25years, the DSPprocessor gets rapid development, but at present domestic use DSP chips are mainly importedfrom abroad and it is bound to have an adverse effect on China’s national security and informationindustry. Therefore, it has become a trend for China independently developing the DSP processorchip into digital signal processing technology.In order to change the DSP chip dependence on foreign products, meet the huge domesticmarket demand, in recent years the thirty-eighth China Electronics Technology Group Institute hasmade special research on high performance DSP processor, and has successfully developed soulcore1(BWDSP100processor) chip. Cache can effectively solve the mismatch of DSP processorspeed and memory access speed, thereby effectively improving the DSP processor computingcapacity. As the DSP processor is becoming more and more powerful, the software programcomplexity is also increasing, software code volume increases rapidly, and at the same time DSPprocessor requires powerful compiler support to achieve a variety of applications, such as loopunrolling optimization compiler performance caused by the instruction code expansion, usinglossless data compression technique in compiled, assembled binary machine instruction code, to reduce instruction code storage space size, so that the DSP processor limited storage spacecondition can store more instruction code, while increasing the Cache hit rate and improving theoverall performance of the BWDSP processing. Instruction Cache design and the instruction codecompressed size become BWDSP processor design considerations.Combined with highperformance BWDSP processor independently developed by thirty-eight Institute of ChinaElectronics Group, this dissertation conducts a study in terms of instruction Cache design,instruction code compression.1) The development of IC process to28nm, high performance BWDSP processor will replacethe foreign DSP processor product. Instruction Cache performance is one of the main factorswhich impact BWDSP process performance, and Cache replacement algorithm is the key factorthat influences the performance of Cache. This dissertation presents PLRU Cache replacementalgorithm. PLRU (Pseudo-LRU) replacement algorithm is in instruction Cache to increase a8bitlru[7:0] vector. When Cache hits a road, it updates the lru[7:0] value; when Cache is missing,according to the lru[7:0] value to determine which Cache block and replaces the update value forlru[7:0]. Through the BWDSP simulator for PLRU, Cache size, Cache block size, set associativemapping simulation, a group of optimal parameters in the instruction Cache are finally obtained.2) High performance BWDSP processor instruction code compression. This dissertationstudies high performance BWDSP processor to jump block code compression unit, using the LZWdictionary compression technology and improved LZW dictionary compression technology to theinstruction code by the compiler and assembler after the formation of binary machine codecompression. The compressed code is stored in the instruction memory, in the instruction memoryand instruction among Cache decoding unit. The method does not need to change the highperformance BWDSP processor compiler, assembler and BWDSP processor core pipeline series.When the instruction Cache is missing, decoding unit to the instruction memory stores acompressed code. The jump instruction code block of the first address to a line address mappingtable (LAT) of a base address, instruction jump block instruction address is LAT base addressplus the offset address. LAT is used to represent the correspondence between compression codeaddress and the address of codes to be compressed, and this will ensure that high performanceBWDSP processor kernel to random access instruction code. In the high performance BWDSPprocessor instruction code compression simulator, the simulation results show that the code rate ataround60%and55%.3) Code compression method based on the execute macro and domain of instruction.Research on domain of instruction code compression method is carried out in this dissertation. Themethod is divided into three steps, which are symbols, symbols generated modeling and symboliccoding. An instruction generating several symbols and symbolic model play an important role for code compression rate. Through the location, type and implementation of macro instruction ofhigher order model this dissertation tries to fully discover the different types of instruction domaincorrelation between internal symbols. Execute macro model and position model are combined intoexecute macro-position hybrid model, and Huffman is used to achieve code compression. Basedon the high performance BWDSP processor instruction set, the high performance BWDSPprocessor development platform authentication code with the Huffman to execute macro-positionhybrid model to generate a symbol code compression, and the compression ratio is about50%.4) To ensure that the high performance BWDSP processor instruction Cache designfunctional completeness, the verification of instruction Cache function based on high performanceBWDSP processor is proposed. Functional coverage is used on the instruction Cache design allfunctions describing conversion. By software emulator model and RTL model instruction Cachefunctional verification test platform is constructed. According to the instruction Cache accessinstruction gets the testing requirements, the coverage report is finally obtained. The results showthat functional coverage rate reaches100%.