Reducing processor simulation time by using adaptive, non-uniform model complexity

As processor microarchitectures continue to increase in complexity, the time to explore the design space defined by them similarly increases. Performing cycle-accurate, detailed timing simulation of a realistic workload on a proposed processor microarchitecture often incurs a prohibitively large time cost. We introduce a method to reduce the time cost of simulation by dynamically varying the complexity of the processor model throughout the simulation. We demonstrate that there are significant amounts of time during a simulation where a reduced processor model accurately tracks important behavior of a full model, and that by simulating the reduced model during these times the total simulation time can potentially be reduced.