SPECS: SIMULATION PROGRAM FOR ELECTRONIC CIRCUITS AND SYSTEMS (CAD, SWITCH-LEVEL, TIMING, MOS)

Simulation tools are central to the development and verification of very large scale integrated circuits. Circuit simulation has been used for over two decades to verify the behavior of designs. Recently the introduction of switch-level simulators which model MOS transistors in terms of switches has helped to overcome the long runtimes associated with full circuit simulation. Used strictly for functional verification and fault simulation, switch-level simulation can only give very rough estimates of the timing of a circuit.;In this dissertation an approach is presented which adds a timing capability to switch-level simulators at relatively little extra CPU cost. A new logic state concept is introduced which consists of a set of discrete voltage steps. Signals are known only in terms of these states thus allowing all current computations to be table driven. State changes are scheduled in the same fashion as in the case of gate-level simulators, making the simulator event-driven. The simulator is of mixed-mode nature in that it can model portions of a design at either the gate or transistor level. In order to represent the "unknown" state, a signal consists of both an upper and a lower bound defining a signal envelope. Both bounds are expressed in terms of states. In order to speed up the simulation, MOS networks are subdivided in small pull-up and pull-down transistor configurations that can be preanalysed and prepared for fast evaluation during the simulation. These concepts have been implemented in the program SPECS (Simulation Program For Electronic Circuits and Systems) and examples of simulations are given.