Research And Design Of Neural Signal Recording And Stimulation System In CMOS Technology

Nowadays,more and more attention is paid to the study of the nervous system.The cause of this trend partly lies in the great sufferings brought by nervous system deseases,and partly lies in our expectation of a deep understanding of the human brain to promote the progress of subjects such as artificial intelligence.Benifited from its characteristics of multi-channels,high data flux,long duration of experiment,and real time performance,the neural signal recording and stimulation system,which integrates microelectronic technology and IC technology,has become a kind of new equipment for study of the network of neuron communities.This dissertation reports on the design of a CMOS neural signal recording and stimulation system for in vitro experiments.The main research contents are as follows:1)The analysis and design of the neural signal recording and stimulation system's architecture is presented.The specifications of the system are analysed and ascertained based on the application background.The specifications of each building block are estimated after a theoretical exploring.The trade-offs of some key specifications,such as noise,power consumption,and cirucit area et al,are consided.Whereafter,the system architecture is designed.2)The electrical characteristics of the neurons are analysed and a model of the electrode-neuron interface is built.The origin,and transport processes of the neural signal are explicated.Furthermore,a model of the interface between an electrode and a neuron is developed.The effects of the parameters in this model are analysed and the result is valuable in the design of micro-electrode arrays and recording/stimulation circuits.Finally,the conclusions of the analysis are compared with the results of the electrode impedance test.3)A novel symmetrical ?-multiplier based resistorless reference with a low power consumption and a low output current is presented.Following a review of the typical module,the reference is designed for the forementioned system.A symmetrical structure is proposed in the symmetrical reference to reduce the excessively length of the MOS-resistor.The circuit is designed in CSMC's 0.5-?m CMOS process,and the simulation results show that the proposed technique is effective in improving the extreme aspect ratio of the MOS-resistor.Meanwhile,the circuit obtains good power supply rejection ratio,low power consumption,low area,moderate line regulation and qualified temperature coefficient when providing a nano-ampere level current reference.4)A novel low noise operational transconductor amplifier based on current mirror topology is proposed.Firstly,the advantages and disadvantages of various amplifiers for neural signal processing are analyzed.Three neural amplifier architectures are introduced which adopting active low-frequency suppression technology or capacitive feedback technology.Secondly,two low noise operational transconductor amplifiers(OTA)are designed for these neural amplifiers.One is a conventional telescopic two-stage OTA and the other one is a new low-noise current-mirror two-stage OTA.The circuits are designed in CSMC's 0.5-?m CMOS process and the simulation results show that the neural amplifiers achieve a low noise,high common-mode rejection ratio,and high power supply rejection ratio.The bandwidth,power consumption and area satisfy the requirement for neural signal processing in experiments.5)A new compact,low power 2nd-order low-pass Gm-C prototype is proposed.Firstly,the integrated active low cut-off frequency filter for neural signal is investigated and the basic context about the categories,the design methods and specifications of the filter are introduced.Secondly,a new compact,low power 2nd-order low-pass Gm-C prototype and a 4th-order low-pass filter based on source-followers are designed.The filters are designed in CSMC's 0.5-?m CMOS process.The simulation results show that the two filters both have appropriate cut-off frequency,satisfactory power consumption as low as nano-watt and small area suitable for neural signal shaping.6)A novel boot-strapped switch with compensation circuit is proposed.The compensation circuit is supplemented to traditional boot-strapped switch based on a study on the constraints on the linearity of the switch.The new boot-srapped switch is designed in CSMC's 0.5-?m CMOS process and the simulation results show that the nonlinear distortion is improved.