Design,Fabrication And Evaluation Of High-robustness Silicon Carbide MOSFET

Nowadays,human production and life are inseparable from electricity.Due to the needs of green development,people pay great attentions to clean and new energy,such as solar energy,wind energy,geothermal energy,ocean energy,hydrogen energy and so on.The conversion of clean and new energy into electric energy is the key way to realize the application of new energy.With the rapid development of new energy technology such as photovoltaic power generation in recent years,clean and new energy have gradually been more widely used.In 2021,China put forward the major strategic goal of striving to achieve carbon peak by 2030 and carbon neutralization by 2060.Therefore,it is urgent to accelerate the practicability of clean energy and build a new power system with new energy as the theme.In the construction of a new power system,power electronics technology serves as the basis for the conversion of electrical energy to act as the skeleton of the system.The most popular field is the transportation field.Due to the carbon neutral strategy,new energy vehicles have begun to gradually replace fuel vehicles.In new energy vehicles,power semiconductors account for about 55%of vehicle semiconductors.As new energy vehicles are sensitive to the price and weight of the on-board charger and the DC/DC system of the power system,a higher frequency(?30k Hz)silicon carbide MOSFET is used to replace traditional silicon devices,which can reduce the heat dissipation system and passive components.The volume of the machine realizes the lower cost of the whole machine.The research and development of SiC MOSFET devices focuses on their specific on-resistance and reliability.In the planar gate MOSFET,due to the relatively fixed structure,the method of reducing the specific on-resistance mainly focuses on reducing the channel resistance by improving the gate oxide process.However,there are still some shortcomings in the current research on the gate oxide improvement process,including ensuring sufficient gate oxide lifetime under the condition of improving the interface state density.At the same time,the application scenarios of SiC MOSFET are becoming more and more demanding,and its reliability has become the focus of attention of researchers.From the comparison of the planar gate and the trench gate,the planar gate MOSFET does not have a gate groove,so its reliability is relatively excellent.In view of reliability issues,it is necessary for manufacturers of power devices to design devices more effectively from both process and structure aspects.At the same time,they also need to have a deeper understanding of the work and failure mechanisms of devices under extreme conditions.Device designers have more effective Device design method.To solve the problems mentioned above,this article focuses on planar gate SiC MOSFETs,and conducts a full range of research from device simulation design,tape-out technology,performance testing,reliability analysis,etc.The significance of this thesis lies in:(1)An optimized gate oxide process was proposed.For the first time,vacuum replacement is used to perform NOx annealing process on the gate oxide in-situ,which effectively reduces the interface state density and improves the channel mobility.In this way,the original specific on-resistance of 1200V SiC MOSFET(8.3m?cm~2)was reduced to 7.9 m?cm~2(cell-pitch 15?m).On this basis,a SiC MOSFET device with a cell size reduced to 9?m and a specific on-resistance of 4.9 m?cm~2 was successfully developed.At the same time,the reliability of the new gate oxide was studied,and the growth and annealing temperature of the gate oxide were further optimized,and an optimized gate oxide process for SiC MOSFET was proposed.(2)It has developed for a set of device structure design,process flow and key process technology development for a commercial 1200V SiC MOSFET.A channel self-alignment process has been developed to make the channel length continuously adjustable from 0.2?m to 1?m;the high-temperature ion implantation process is optimized to increase the activation rate of the P+region at high doses,and effectively reduce the implantation Defects,increase the lifespan of few births.(3)It is the first time to presentthe optimization of SiC MOSFET structural parameters for device threshold voltage shift,short circuit withstand capability and surge withstand capability.The threshold voltage drift is reduced by reducing the channel doping concentration;the best matching point of the conduction performance and the short-circuit withstand capability is obtained by selecting the appropriate JFET width and channel length design.By reducing the channel doping concentration,the channel opens with the body diode in advance during the surge process,thereby increasing the surge withstand capability of the device.The research methods proposed in this thesis,such as device design,process tapeout,and reliability analysis,provide a complete set of device development process for device researchers.Through these methods,device design can be accelerated,and device reliability can be evaluated and improved in time by the help of this thesis.