Reach On The Key Technologies In The Low Power Rf Transceiver Chip For WSN

Wireless Sensor Networks(WSN)technology is the technical support for the Internet of Things.It combines advanced technologies such as computers,communications,sensing,and microelectronics.It is widely used in many fields,such as industrial control,smart home,consumer electronics,military security,logistics,intelligent precision agriculture,environmental awareness,and health monitoring.The wireless sensor network node is an important unit of WSN,each node needs to have the ability of sensing,data processing,and wireless communication.The low-power wireless radio frequency(RF)transceiver chip is of great significance for the efficient transmission of information between nodes,reducing the size of the node,and reducing the cost of the node.How to reduce power consumption and noise are the two most critical issues that need to be solved in the design of WSN node wireless radio frequency transceiver chips.In the existing solutions,there are many power supplies in the core circuit of the wireless transceiver,leading to multiple conversion losses.These power supply voltages are high,which brings greater energy loss.The overall power consumption of wireless transceiver can be reduced by optimizing the power management circuit;besides,the phase-locked loop and low noise amplifiers are two modules with higher power consumption in wireless transceiver chips.Reducing their power consumption can also greatly reduce the power consumption of radiofrequency transceiver chips.The spurious and phase noise performance of the phaselocked loop(PLL)and the noise performance in the low-noise amplifier have an important influence on the sensitivity and bit error rate of the RF transceiver chip.Therefore,to ensure the high performance of the wireless radio frequency transceiver chip,while reducing its power consumption,in-depth research and careful design of phase-locked loops and lownoise amplifiers are also required.The low-power management module includes a boost converter,LDO regulator and a low noise bandgap reference.To reduce the power consumption of wireless transceiver chips,this thesis reduces the output voltage of the boost converter.An adaptive on-time control technique is proposed,reducing the output voltage ripple in discontinuous conduction mode with pulse frequency modulation.To reduce the start-up voltage of the boost converter and the whole system,this thesis proposes the subthreshold start-up technology.The traditional low dropout linear regulator is difficult to work at low voltage,which limits the reduction of boost converter output voltage.To solve this problem,this thesis uses a low-voltage structure,so that LDO can work under 1 V supply voltage.The wireless transceiver chip needs a voltage reference to provide accurate bias voltage.This thesis proposes the offset and noise cancellation technology,and uses the piece-wise compensation technology.Then the accuracy of the reference voltage can be improved.To reduce power consumption of the RF transceiver chip,the low-voltage high-performance PLL designed in this thesis works at 0.8V supply voltage.The sensitivity and the bit error rate of the RF transceiver chip is improved by optimizing the phase noise and spurious of PLL.The phase noise performance of PLL is determined by the phase noise performance of voltage controlled oscillator(VCO).To improve that,a class C VCO with dual digital feedback loops is proposed.The dual digital loop enables the VCO to work at 0.8V supply voltage,which reduces the power consumption of the VCO.Besides,it avoids the noise introduced by the analog loops and improves the phase noise performance of VCO and thus PLL.To further improve the phase noise performance of VCO,this thesis also proposes an adaptive bias technology.The spurious performance of PLL is affected by the precision of current replication in the charge pump(CP).The resistance based current replication technology is used in this thesis for improving the spurious performance of PLL.To reduce the power consumption and improve the sensitivity of RF transceiver chip,a lownoise power amplifier(LNA)with transconductance calibration technology is proposed.This thesis adopts passive load technology and on-chip balun feedforward technology,reducing the power supply voltage and power consumption of low noise power amplifier.This thesis adopts the subthreshold bias technology,which further reduces the power consumption.To weaken the transconductance variation in the sub-threshold region,which is caused by the process and temperature variation,this thesis proposes a transconductance calibration technique.In this thesis,some of the key unit circuits of the designed RF transceiver are tested,and the rest of them are verified by circuit simulation and post-layout simulation.Compared with the traditional power management module,the customized power management module designed in this thesis can save at least 61.5% of the power consumption.The test results show that the boost converter of the power management module can start normally under the input voltage of 300 mv-800mV,providing 1V power supply voltage for the subsequent circuit,and its peak efficiency is 90.6%.LDO can operate at 1V supply voltage and produce0.8V output.The proposed VCO achieves a phase noise of-123.3dBc/Hz at 1MHz offset from a 2.55GHz carrier.The proposed PLL achieves a frequency tuning range of 2.24-2.85GHz and phase noise of-123.97dBc/Hz at 1MHz offset from a 2.55GHz carrier.At an offset frequency of 40MHz,the measured reference spur is-89.4dBc,and the total power consumption is 2.62mW under a 0.8V supply voltage.Finally,this thesis carries out circuit design and post-layout simulation verification of the designed LNA.The simulation result shows that the noise figure is 2.86dB,the third-order input intercept point is-15.9dBm,and the minimum power consumption of the circuit is 543.6μW.