| Arc faults in the power system may cause significant damage to equipment,even lead-ing to electrical fires and personnel hazards.The traditional circuit breaker cannot timely and effectively identify the series arc fault,and it cannot locate and isolate.Therefore,the design of System-on-Chip(So C)dedicated to series AC arc fault detection and location has important research and application value,and can also improve the integration of arc fault detection system,reduce costs and power consumption.This thesis concentrates on the acquisition,detection and location of arc faults,ad-dressing key technology research,key modules and algorithm implementation,and system integration and development.It proposes a low-cost,low-power So C for series arc fault de-tection and achieves arc fault location using the chip platform.Specific research contents and innovations are as follows:(1)Aiming at the requirements of the arc fault detection So C for clock generator which can ensure high-precision acquisition,real-time detection and rapid response of arc faults,a high-performance all digital phase-locked loop(ADPLL)based on a new dual-tuned dig-itally controlled oscillator(DCO)is proposed.The DCO adopts a digital-to-analog con-verter(DAC)control array scheme with a coarse-tuning stage and a fine-tuning stage.The whole circuit not only achieves low jitter and fast locking,but also does not require any additional circuits and can fully automatically place-and-routed.It has portability and low hardware overhead,and can greatly reduce the chip area.Using the proposed dual-tuned DCO,this thesis completes a high-performance ADPLL under the standard 55 nm CMOS process with a chip area of 0.001 mm~2.The experimental results show that the designed ADPLL has a power consumption of 112.32μW at a 1.0 V power supply voltage,and can realize fast locking in 55 reference clock cycles.When the input reference frequency is10 MHz and the pre-divider output frequency is 100 MHz,the RMS jitter is 14.4 ps,the reference spur is-48 d Bc,and the phase noise is-82.06 d Bc/Hz at 1 MHz frequency offset.(2)Aiming at the requirements of the arc fault detection So C for low cost and low power consumption arc fault acquisition circuit,the high performance successive approx-imation analog-to-digital converter(SAR ADC)is researched and designed.In order to reduce the number of unit capacitors and reduce hardware overhead,a low power and low cost four-segmented capacitor array is proposed,and a SAR ADC is implemented based on it.The converter is verified under the standard 55 nm CMOS process with an area of0.0256 mm~2.The power consumption is 34.73μW,and the SNDR is 57.16 d B.In order to further improve the conversion accuracy,the thesis improves the capacitor array,and the redundancy technology without adding additional redundant capacitors,as well as the tech-nologies of dynamic element matching and capacitor swapping are adopted.A calibration free high-performance capacitor array DAC structure is proposed,which meets the high precision requirements without additional calibration circuits.The circuit structure is sim-ple,with low hardware overhead,and reduces design and manufacturing costs.The DAC is also implemented under the 55 nm CMOS process.Compared to the four-segmented ca-pacitor structure before,this design does not require additional calibration circuits,and the SNDR can be improved by 16 d B.The SAR ADC realizes a Fo M_Sof 161 d B and occupies an area of 0.13 mm~2.(3)Aiming at the requirements of the arc fault detection and location system for small size,low power consumption,low cost and high integration,a voltage and current dual domain So C for arc fault detection and location is designed.The main features include:a)The arc fault signal acquisition circuit based on SAR ADC can simultaneously acquire volt-age and current signals in low-voltage distribution systems?b)The clock management unit based on ADPLL can ensure accurate acquisition,real-time detection,and rapid response of arc faults?c)A voltage and current dual domain arc fault detection algorithm is pro-posed,which extracts the features of arc fault voltage and current signals through discrete wavelet transform,and compares with the thresholds.Based on the comparison results in the current domain,arc faults can be determined,and then based on the comparison results in the voltage domain,fault branches can be distinguished.The So C is verified under the standard 55 nm CMOS process.The test results show that the chip can rapidly detect the arc fault within 80 ms,and the recognition rate is 97.5%.At the same time,according to the abnormal conditions in the acquired voltage signals and current signals,the arc fault branch can be distinguished.(4)Aiming at the requirements of the arc fault detection and location system for low cost and rapid arc fault location method,a successive approximation fault location algo-rithm based on impedance ranging method is proposed.While meeting low-cost require-ments,it can rapidly locate the fault,providing the possibility for the power system to locate series arc faults in operation mode.Combined with the So C of arc fault detection and lo-cation,an application model of arc fault detection and location in multi-branch complex low voltage distribution system is proposed.The thesis analyzes the equivalent model of distribution lines with series arc faults,and based on the implemented arc fault detection and location So C,establishes the location equations of distribution line fault location and current and voltage signals.Based on the idea of successive approximation,the fault in-terval is quickly determined,and the fault point is determined according to the set search accuracy.This algorithm is modeled and simulated in Matlab to test the relative location error of different distribution line lengths and fault locations,as well as the fault location results under different noise conditions.The results show that when the signal-to-noise ra-tio is greater than 45 d B,the relative location error is still less than the set search accuracy of 1%. |
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