Design Of Fully Integrated Phase-Locked Loop For GPS Receiver

GPS receiver finds widely applications in modern society, and PLL is the one of the most important blocks in it. PLL provides accurate local oscillating signals for mixer. PLL is one of the most challenging blocks in analog and RF design. The PLL designed in this paper uses a charge-pump which is popular at present, including analog block-charge pump, RF block-LC tank VCO and digital block-frequency divider.The paper presented a fully integrated charge-pump PLL for the GPS receiver based on SMIC 1P6M 0.18um technology. First, the behavior characteristics of the charge-pump PLL was studied, the models in phase and voltage domains of the PLL were built by using Matlab, and the model in voltage domain of the PLL was wetup by using Verilog-A. In the design process of the charge-pump, an Opamp was used as an error amplifier, and since the negative feedback was employed, perfect current match was reached in a large range of the output voltage. The phase noise models of the LC tank VCO and the phase noise reduction technology were also investigated, a LC tank VCO was designed, its output frequency range is from 1.35GHz to 1.5GHz, gain is 139MHz/V, and phase noise at 600KHz is -118dBc/Hz. Finally, a fully integrated PLL was designed, the fraction number of frequency divider is 70 at 1.4GHz, additionally, the frequency divider operated at higher than 5GHz was discussed in this paper, and an integer-5 divider working at 5GHz was design. During the design of the PLL, The phenomena such as cycle slipping and the coupling between 2^nd harmonic of output signal and control voltage of the VCO were discussed. The layout and post-simulation of the PLL were completed in this paper, The PLL provides three local oscillation signals, their frequencies are 1.4GHz, 140MHz and 31.111MHz respectively, the reference frequency is 20MHz. the unity gain bandwidth of the PLL is 280KHz, and the lock time is less than 10us, the power of the PLL is 10mw. The spurs is -65.7dBc, the phase noise at 1MHz offset is less than -120dBc/Hz, the area of the layout is 600um×700um.