IP Soft Core Design Of Digital Servo System

According to the anxious requirement of the information technology and the wide application of AC motor, IP soft core of speed servo system for AC drives based on vector control strategy is designed. This IP soft core includes current PI controller, speed PI controller coordinate transform module, speed measurement module and SVPWM module. And it not only can be applied as a module, but also can be widely applied in system level chip design.The project uses "Top_down" technology to develop core by dividing system according to it's function. At first, design and simulate on single module, secondly, on the whole system, at last verification using FPGA. The results proved the design scheme is reliable and perfect on function.There are six sections in the whole thesis. The third, fourth, and fifth sections are emphases of the project, these sections mainly describe how to design the IP soft core.The first section, the necessity of designing the IP soft core of digital servo system is discussed by analyzing the actuality of the servo system development and the application of AC motor controller, and proves that it has science and economy significance.The second section, the vector control strategy of AC drives and the SVPWM principle are analyzed deeply.The third section, how to design is introduced according to the idea of the design. At first, the function index is introduced. Secondly, The digital speed servo system is divided into several modules. And the design schemes of the modules are discussed. Atlast, the digital realization of CORDIC arithmetic and SVPWM module is discussed in detail. The results indicate the loss of switch can be reduced in effect.The fourth section, the simulation charts of the modules are given. The last simulation charts are given to prove the right of design.The fifth section, Verilog language is used to code the code. The functional and time stimulation use the MAXPLLS II. First, each module is simulated. Then, after the right result comes out, the code of each module is assembled to form the code of whole system. Last, the whole system is simulated. FPGA is used to verify the function of the system. The FPGA chip used is epfl0k30R208 of ALTREA. The configure file is downloaded into the FPGA chip according to the FPGA design flow. Then the outputs are observed by oscillograph and compared with the simulation results, indicating the design can meet the requirements in advance.The sixth section, sum up the works, harvest and what one has learned. And give a future view about the project.