Research On Two Stage Converter Applicable To Future VRM

The rapid developments of the CPU call for more stringent requirements to the VRM. To reduce the bus loss, the VRM input voltage increase from 5V to today's 12V, and predicted to increase to 48V in the future. While the output voltage will be lower than 1V, the load is about to be more than 200A. So, in such application case, traditional converter can hardly serve the demands well. A novel topology is needed to meet the higher and higher requirements. This paper analyzes the challenges for the future VRM, summarizes the key problems in designing. As a solution, the "HB(D=50%)+Buck" structure is brought forward. This structure has such advantages: high efficiency, high power density, and simple control. The system stability & the design of filter and PCB transformer were discussed in this paper. Then a 1/8 brick module is built to verify the analysis. Besides this, we make some improvement to resolve the shortcoming of "HB(D=50%)+Buck" structure. The Interleaved Multi-phase Buck converter is introduced to the structure to reduce the thermal stress and improve the transient response. The design of compensation loop and AVP control are discussed. Also, the simulation and the experimental results are given to verify the analysis.