Study On Impiementation Of CMFB Based Transient Current Protection For EHV Transmission Line

It is of importance to the security of the power system to ensure the reliability of HV/EHV transmission line protection, so searching for a new protection theory and it's efficient method is a main task. There are many superiorities in the processing of fault transient signal applying multi-rate consine modulate filter banks. But there are many difficult problems, for instance how to implement the multi-rate consine modulate filter banks efficiently, and how to assure the protection arithematic is real time? The methords about implementation of protection basing on multi-rate consine modulate filter banks, especially, the IP core of the arithmetic, was studied in the thesis.There are some preliminary fruits and conclusions as follows:1. The influence of generatrix to the transmit of transient currents was acquainted through studying the characters of transient currents applying multi-rate consine modulate filter banks. We got the best time window after study the time distinguish ratio of transient currents energy. The energy can be calculated out basing on the signals decimated, and the energy ratio was carried out directly, and we were astonished to find out that the fault character was not affected. All these finds was helpful to the implementation of project.2. Considering the parallel structure of multi-rate consine modulate filter banks, analysis filters was divided into parallel multiphase form, and the long filters were translated into short multiphase filters, hence, the system speed was advanced highly. Furthere more, analysis filter with decimator was transformed equivalently to, and the high efficient structure was designed out, the strongpoints were that redundancy calculation was eliminated, and that calculation times was decreased sharply, and that efficiency was increased highly.3. In terms of the real time need of transient current protection, the IP core scheme of transient current protection arithmetic was studied. After studying DA arithmetic, the filters coefficient were divided into many segments in order to forming ROM tables for the purpose of saving hardware, and full pipeline parallel structure wereadopted for bit level looking up table, which making the highest speed, and the multiplication operation was translated into looking up table operation. After whole IP core project scheme maded, modules were implemented one by one using VHDL, in the end, all modules were integrated into a whole system. Finally, stratixll servering as target chip, the system was synthesized applying synplify, simulated and timing analyzed applying QuartusII, and validated using MATLAB.