The VLSI Implementation Of 2-D DCT And Its Soft Core Design

With the rapid development of remote-sensing technologies and the increasing demand of better Image quality, the resolution and sample rate has become higher and higher. The total code rate becomes as much as 2000Mbps. So, there has been a great demand of an effective approach to compress the data. Due to national economy and security, we should develop our own powerful, low-power, small-volume and highly reliable information systems for our satellite SOC. On the other hand, the main task of SOC development is to create our own IP (Intellectual Property) cores. Because the DCT has been widely used in image and video compression field, to develop a reusable DCT IP core is very important and valuable. Based on the above idea, this paper summarizes the most popular DCT fast algorithms and their VLSI implementation architectures. Then,a no-multiplier, DA based, pipelined DCT hardware architecture is presented. The Verilog HDL source code is developed, and the functional simulation is completed. Afterward, according to the design requirement of IP soft core, we implement this DCT IP core on several kinds of FPGAs, and map it on to UMC0.35um standard cell library, which increases the reusability of this IP core. Finally, the paper compares this DCT IP core with some industry products, which gives our future work more experiences and firm foundation.