The Design Oftax Electronic Cash Registe System For Garfield Processor

It should not only focus on the SOC chip in the research of SOC. The research of theSOC System is an important part of SOC .It could widen the application range of the SOCand guide the development of the chips.The Tax ECR was a new industry that promoted by the"gold tax"project which would bewidely used in the several years. There were some defects on the Tax ECRs that were on sale.One was the lack of interfaces and other was expansibility of the system. In this paper, theresearch focused on the implementation of Tax ECR system, which based on the SOCGarfield SEP3203 and featured on multifunctional and expansibility.The Garfield SEP3203 processor was the core of system, and FPGA used as interfacecontroller. There were parts in the system. One was the processor application system; otherwas the FPGA extended system. The processor application system had two parts too.One wasthe memory system and other was periphery interface system. Design the memory systembased on the analyzing of the requirement of the memory system and the shortcoming andmerit of many different memorys. Designed real time system and calculated the natural life.Designed the Ethernet controller and USB OTG controller by bus extended. It finished thepower system the circuit in the end.FPGA extended system contained IC/SIMcard controller, printer driver circuits, VFD,PS/2 controller, 1284 interface and Standard RS232 interface. Finished the communicationinterfaces between processor and FPGA by utilizing the SRAM interface. It designed andoptimized the printer driver circuit and designed the IC/SIM ciontroller periphery circuits inwhich some singles were common used. It designed the PS/2 controller that concluded theperiphery circuits and interal module based on the PS/2 protocol.At the end, Debugged the FPGA extended system that included the printer controller,IC/SIM controller and PS/2 controller. In addition, it got the system performance parametersafter test. The error of the real time system was below±1s per day. The Ethernet data rate was100Kbps~500Kbps in test and The USB OTG controller's rate was 3.97Mbps. Printer couldwork in the rate of 2.4 rows per second. The IC/SIM controller could work at the rate of9600Kbps. The maximum clock rate that the PS/2 controller could support had aboved 1MHz.By now, the sample machine has been finished which contained a complete demoprogramme.Compared with other congener systems, it added Ethernet controller and USB OTGcontroller in the design, and used FPGA as extended system. It had proved that its interfacesort and expansibility priored to the other congener design and achieved the goal.