Development Of Digital Storage Oscillograph

1. The meaning of this paper's researchDigital storage oscillograph can easily carry on the observation to random signal. Analog oscilloscope is excel to measure periodicity signal, but it is hard to observe random signal. The general communication engineering specialized laboratoris all have analog oscillograph, do not equip digital storage oscillograph, so the random signal in experiment cannot to be observed. Analog oscillograph is normal metering equipment, cannot be eliminated. In this paper, analog oscillograph is reformed to digital storage oscillograph but not modifing the analog oscillograph's internal structure. Aanalog oscillograph is used independently.2. Targets of operating and measuringThe targets are completing hardware circuit manufacture and producing measuring result. Software design: the part of FPGA programme using VHDL hardware description language, the part of monolithic integrated circuit programme using MCS-51 assembly language. Before hardware design the theoretical simulation must be carried on using MATLAB. The digital storage oscillograph can measure 2MHz square-wave.3. Simulation of digital storage oscillograph(1) Simulation frame diagram of digital storage oscillosgraphSimplifid block diagram of digital storage oscillograph composition shows in figure 1. Simulation is carried on according to the block diagram. Figure 1 Simplified Block diagram of digital storage oscillograph composition(2) Analysis of simulation results According to the simulation, the square-wave has overmodulation phenomenon of time domain after it passes the amplifier, and its rise edge with drop edge is not Input signal Amplifier of weaksignal A/D RAM D/AControl logicalgorithm 8bit 10bit Output signal steep. The factual amplification circuit also have this kind of phenomenon. After passing A/D and D/A, the waveform converted by smooth filter is relatively smooth, the level transition region becomes smooth, the waveform losts the partial high frequency components. But this phenomenon cannot result the serious distortion of time domain, it can be acceptted in time domain.(3) Hardware design referring to simulation result The simulation result mentioned above showes that:①Simulation block diagram is feasible. Hardware circuit of digital storage oscillograph may designed according to the simulation block diagram.②Amplifier channel bandwidth of digital storage oscillograph hardware's front end is bigger than the harmonic bandwidth of measured signal harmonic component which amplitude is 10% of base waveform.③Sampling rate is 2 times above the harmonic frequency of measured signal harmonic component which amplitude is 10% of basel waveform, so the waveform has very good reappearance.④2MHz square-wave is measured. Its 9 order harmonic is 18MHz, so the amplifier channel bandwidth is bigger than 18MHz. 20MHz is taked. Sampling rate should be bigger than 40MHz, so sampling rate is 100MHz.4. Parameter of digital storage oscillograph hardware circuit(1) Amplifier channel bandwidth is 200MHz. It is the equivalent sampling rate reserved.(2) Sampling rate is 100MHz.(3) Resolution is 1/256, namely 8-bite A/D converter.(4) Storage depth of single channel is 32K.(5) Real-time reappearance and storage reappearance can be carried on.(6) Resolution of display is 1024×1024. Reappearance uses 10-bite D/A converter.(7) The circuit has double channel, the X-T display mode and the X-Y display mode.(8) The circuit reserves commnication interface with computer RS-232.5. System design of digital storage oscillographOverall functional block diagram of this paper shows in figure 2. After weakened and amplified by front end of the system, the input signal enters the A/D converter AD9288. XC3S200 FPGA as the master control logic, controls AD9288 to carry on A/D conversion. The converted data saves in the double port RAM of FPGA or in exterior memory T35L6464A. When needing reappearance, FPGA delivers the data to the D/A converter and controls DAC900U to carry on the D/A conversion. Passing through the amplifier OPA650U of rear end , the converted signal is amplified to suitable amplitude and reappeared on the analog oscillogaph.6. Function module design of digital storage oscillograph(1) Master control module design SPARTAN-3 XC3S200 FPGA of XILINX Corporation is choosed as master control chip. Its internal clock is up to 326MHz.Its application in this design as follows:①Controls A/D converter to carry on analog/digital conversion.②Controls T35L6464A memory to carry on data read-write operation.③Controls D/A converter to carry on digital/ analog conversion.④Reserves RS-232 interface⑤Has 10-bite communication interface with MCS51.(2) A/D conversion module designThe conversion speed of AD9288 is 100MHz. Application circuit of AD9288 in digital storage oscillograph shows in figure 3. (3) Storage circuit designStorage depth of single channel must be 32k byte. T35L6464A-5Q memory is selected as exterior memory. Its capacity is 8×64K byte. Its storage time is up to 5ns. Block memory in XC3S200 FPGA is selected as high speed dobule port RAM. Its redundant capacity serves as data processing memory. Aapplication circuit of T35L6464A in digital storage oscillograph shows in figure 4. (4) D/A switch and back end amplifier designDAC900U is 10-bite D/A converter. Its conversion speed is 165MHz. It can carry on real-time reappearing. Reappearance resolution is 1024×1024 spot without smoothing filter. The application circuit of DAC900U in digital storage oscillograph shows in figure 5.Output amplifier uses OPA650. Its bandwidth may be 240MHz. Application circuit of OPA650 in digital storage oscillograph shows in figure 6. DC13 2.2uF (5) Input circuit designInput attenuator designs using RC set. Iinput resistance is 1MΩ. Bandwidth of input amplifier AD8001, is 880 MHz when G=+1, is 440 MHz when G=+2. 3dB bandwidth is 200 MHz When G=+10.7. Circuits board welding Handmade welding starts under the magnifying glass. Static electricity must be avoided. The completed circuit board shows in figure 7.8. An example of resultOriginal input square-wave shows in figure 8. The square-wave of storage reappearance shows in figure 9. The actual square-wave is 2MHz. Explain: In order to be advantageous for debugging and comparing, the procedure has a little modification that causes the waveform of storage reappearance to be truncated to sections, distinguishes from the measured original waveform.9.Summaries(1) Completed tasks Development of digital storage oscillograph is synthesis design of software and hardware. Completed tasks are:①Designed functional block diagram of digital storage oscillograph.②Ddrawed up 4 layers circuits board of digital storage oscillograph.③Finished welding and manufacture of digital storage oscillograph hardware circuit.④Accomplished programming and debugging of master software on ISE software using VHDL language. Accomplished programming and debugging of monolithic integrated circuit programme using MCS-51 assembly language.⑤Completed synthesis debugging of oftware and hardware. Fulfilled the digital storage oscillograph basic function. The test results show the digital storage oscillograph developed in this paper can store and reappear 2MHz square-wave. The digital storage oscillograph has achieved requests proposed by this paper.⑥Carried on model simulation of digital storage oscillograph before hardware design, obtained reference targets of hardware design.(2) Insufficiency and future research direction Observed from the factual waveform, measured waveform has the periodicity noise spot. The reason is the operation of FPGA procedure causes power distribution imbalanced, creates undulation of power supply, causes error codes. Selectinge high quality capacity of power supply filter should effectively suppress power supply undulation. At present the OS-CON capacity samples is applied from SANYO electric capacities business agent. According to the capacity performance, this kind capacity can suppress power supply undulation.As a digital storage oscillograph, input bandwidth, sampling rate and storage depth of its front end are three most essential requirements. The technology at present has method to enhance sampling rate and increase storage depth. Enhancing input bandwidth of front end is future study direction.