RFID-based Highway Electronic Toll Collection Design And Research

While devoting major efforts to the development of intelligent transport systems, state proposes the development requirements for the no-stopping Electronic Toll Collection (ETC). In this case, according to the development requirement, basing on systematically analyzing the state announced new standard for Dedicated Short Range Communication (DSRC) and comparing the DSRC with other countries', this paper designed an ETC system which adapted to the development of our country's traffic. This paper mainly researched the physical layer and data link layer of the DSRC standard. The physical layer of the system adopted software defined radio architecture, which could well solve the compatibility problem between two types of devices A and B in the DSRC protocol, and could benefit system update and function improvement update. The two types of devices A and B adopted ASK and FSK modulation scheme respectively, so the A and B type compatible device must be capable to identify ASK and FSK modulation schemes. Therefore, the A and B type compatible device adopted orthogonal demodulation scheme to demodulate ASK and FSK signal, that is, the signal is decomposed into two parts I and Q through which the amplitude and phase information can be obtained and then the purpose of demodulation and mode identification was realized. The intermediated frequency processing on physical layer was done in FPGA. According to the standard, data link layer adopted HDLC communication protocol. Based on the analysis of the protocols on each layer, the hardware platform for ETC system was realized. This platform is composed of ARM and FPGA. FPGA is mainly applied for intermediated frequency processing on the physical layer of a system, that is, quantizing the received analog signal with A/D to get the digital intermediated frequency signal, outputting the demodulated digital intermediated frequency signal, and outputting the analog intermediated frequency signal through D/A after modulating the baseband signal at the same time. Besides completing DSRC standard based data link layer, ARM processor realized USB communication with upper computer, providing a good platform for the subsequent application layer design.