Design Of Low Power PFC Chip Circuits Without Multiplier

With the rapid development of electronic technology, more and more electrical equipments are connected to the power network.So that the harmonic current will be introduced in the AC power supply system. However the harmonic currents will cause a lot of negative problems, such as voltage distortion, thermal noise, and reduction of the capability of the power energy transmission line. Power Factor Correction is an effective technique for improving this problem. This thesis focuses on the demands of the small power market, using TSMC 1μm 24V processes for the design of XW8201, which is a power factor correction chip worked in a critical conduction mode.First, this thesis has outlined the PFC technology principle and the development, and then several basic APFC circuit's topologies are intrduced, and a detailed analysis and comparison of circuit control mode for two APFCs with common critical conduction mode are presented. Based on the analysis above, the system design, circuit design, and simulation have been completed. With a boost CRM active power factor correction, the electric current is automaticly followed with voltage. The prominent advantages of proposed design are that the chip is achieved without the traditional circuit's input voltage multiplier circuit and the sampling circuit, and the chip size and complexity are greatly reduced. In view of the shortcoming of the traditional power factor correction chip in slow transient response, the multi-output vector error amplifier is developed with low band width filter function and the fast smooth output transient response ability. Moreover an optimized electric circuit is added in chip interior to increase conduction time of the power switching at input voltage crossing zero, to optimize input alternating current THD and further improve the power factor. In addition the biggest programmable maximum on-time techinique is used, so that it is suitable for user to set up the biggest conduction time according to their actual needs, thus the chip application is more flexible.Finally chip design is simulated and verified by Cadence with TSMC high voltage model (1μm). The results indicate that the proposed design meet with all the design specifications and have a perfect Power Factor controlling performance.