Design Of A Boost Active Power Factor Correction Circuit

In recent years, people pay an increasing attention to harmonic pollution of powersupply, and require power system that have characteristics of low harmonic and highpower factor. Furthermore, many international standards strictly limit harmonic contentthat are produced by electrical appliances or nonlinear loads. Active Power FactorCorrection (APFC) is an effective technique for restraining harmonic current andincreasing the power supply network efficiency. With the stricter quality requirement ofelectric equipment, this technique has been widely applied.The topic about the thesis is the corporation with an abroad company. A boostmode active power factor correction circuit using EPISIL DF1 5μm 40V BJTtechnology is presented in this thesis. In order to meet the requirements, the current ofinductance is controlled with critical conduction mode in this thesis. The input supplyvoltage is 220V alternating current which frequency is 50 hertz. The maximum outputpower is 100W, and its output voltage is 410V with 9V output voltage ripple. Thiscircuit can operate in the temperature rage of-25℃to 125℃. It also includes overvoltage protection and under voltage lockout with 3V of hysteresis, protecting the loadand the circuit during fault conditions. It is suitable for Electronic ballast, SMPS andother applications.In this thesis, the characteristic of DC-DC basic converter and the control methodof active power factor correction are analyzed and compared firstly. Then, the wholechip diagram is proposed according to the design specification and the whole chip'soperational principle is introduced. Based on the whole chip function requirements,sub-blocks design and simulation are completed, including band-gap voltage reference,voltage bias, zero inductance current detection and under voltage lockout. At last, thewhole chip function simulation and some typical performance characteristics simulationare presented. In the conclusion of this thesis, the research value of this circuit ispointed out, but it is suggested that comer simulation and post-layout simulation shouldbe indispensable.This thesis is a production of circuit principles and simulation practice. Based on the circuit principle analysis, the author simulated the sub-block circuits and the wholechip circuit by applying the EDA tool HSPICE. The simulation results indicate that thecircuit has achieved the design specification. Furthermore, the circuit principle analysishas been verified. Although there are unavoidable disadvantages of this project, it is aworthwhile and valuable experience.