24V-Input, Wide Output Range, High-efficiency Buck DC-DC Converter Design

The circuit and layout designing of a high-voltage DC-DC converter IC is presented in this paper. The input range of this converter is 5.5～24V, output range of it is 1.2V～V_DD·90%The circuit design flow of DC-DC converter and the main steps of designing is summarized. The first section is the basic theory of DC-DC converters. The second section is about the behavior model of the circuit and the stability analysis in the frequency domain. Circuit designing of sub-circuits is presented in section three. The fourth section is about high-voltage layout notices. In all, the simulation result is acceptable according to specification, and the layout is taped out.The control method of this chip is PWM/PFM dual-mode DC-DC control, in which, the PFM mode is implemented with novel minimum-duty-cycle control. In this control method, the duty-cycle is always greater than the minimum duty-cycle limit. When output current is very small, even the minimum duty-cycle is larger than needed, so if there is pulse output voltage will rise. When output exceeds pre-defined output too much, OSC pulse will be disabled. Therefore, there will be only one pulse in several periods. Consequently, it works as a pulse frequency modulation. The advantage of this control method is that the power consumption is significantly reduced while output ripple remains small.A novel frequency domain testbench of DC-DC PWM control loop is also built. This testbench used a normalized modeling method. The real analog sub-circuit and load components can be tested directly in this testbench, and their effects on loop gain and phase margin can be seen. Using this testbench, we successfully designed the frequency conpensation method of the DC-DC chip.A minimum duty-cycle generator is designed too. The switching point between PFM and PWM mode is decided by the minimum duty-cycle. Therefore, the minimum duty-cycle must be proportional to stable duty-cycle of PWM. Using this sub-circuit, minimum duty-cycle is proportional to output voltage and inverse proportional to input voltage. Since PWM duty-cycle works in the same way, they can track each other in wide input/output range.A new slope compensation current generator is also introduced, which generate slope compensation current proportional to the output voltage, making PWM loop stabler in wide output voltage range.We also discussed some high-voltage layout methods and notices.This chip is designed with TSMC 0.6um 40V BCD process, simulated with Cadence Spectre simulator. Chip works stably in the pre-defined input/output voltage range. On 1mA to 1A load regulation, peak error of output voltage is below 5%, on 19V to 24V line regulation, error is below 1%.