Research And Design Of Low Loss DC/DC Buck Converter

In recent years,as the increase of the consumer electronic products, such as cell phones.the demand of power management chips is growing faster and faster.Meanwhile, consumer devices, which belong to the energy limited power system has become a new challenge to the development of the power management field. So efficient power management design has become a serious factor in nowadays' research. And this is why this research on the synchronous'Buck DC/DC conveter is concerned about.My work is design a synchronous' rectifier' Buck DC/DC converter IC solution. For the consideration of the digital CMOS process has bebecoming the main process in SoC designing, the topic of this thesis is : The analysis and design of low loss Buck DC/DC converter based on standard digital CMOS process (SMIC 0.35um Logical CMOS process).This thesis analyzes different kind of DC/DC converter's solutions and the feedback methods.And then, we have determined to use the Buck DC/DC converter ,with the voltage PWM feedback control's toplogy as our design to achieve an accurate dynamic and static output character.Based on our design SPEC, from choose Buck DC/DC converter's parameter ,we finally got a low lossless power converter with a bandgap reference to insure the minimum disturbance under thevarying of the input voltage. Furthermore, the thesis show a lossless folded cascade amplifier, and low power driven circuits.The thesis analyzes the common problem of the Buck DC/DC converter.the unstability and starting current surge phenomenons.According to the problem above ,the thesis adds the Feedback compensation net and softstarting circuit to settle them .Then we use synchronous rectifier circuit instead of the diode of the traditional Buck DC/DC converter, and use the corresponding rectifier's driver circuit to lower the powerloss of the converter.And finally from the simulation,we achieve a high efficiency Buck DC/DC converter with a good output performance.