The performances of the phase-locked synchronous circuit play an important role in the precision of synchronous data acquisition with power quality data acquisition card. This paper firstly designs a DPLL based on FPGA, which can adjust proportional and integral coefficients. The designed DPLL can error-freely track the phase step and frequency step signals, and can meet the requirements of data acquisition. Secondly, this paper puts forward a method of phase failure detection and loselock judgment based on FPGA. The proposed method can make the correct judgment when signals break or the DPLL loses lock, and switch the output to the locked phase signal rapidly. Finally, this paper puts forward a signal denoising method based on mathematical morphology filter and wavelet filter. The method effectively eliminates the harmonic components, white noise and random pulse contained in the signals.
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