Research And Design Of High Performance Programmable Charge-pump Phase Locked Loop

With the development of modern electronics, communications and other technologies, people require higher and higher performance of Phase-Locked Loop. In order to improve the level of domestic IC design and consider the application from defense to commercial field, it's really necessary to develop our own high- performance PLL product. In this paper, to design the frequency synthesizer used in high-performance DSP, the basic theory and overall structure of PLL have been introduced first, then PLL parameter design, noise performance estimation, circuit design and simulation have been completed. In this way, a high performance programmable Charge-Pump Phase-Locked Loop (CPPLL) has been designed and implemented by Charter 0.13μm mixed-signal CMOS technology using the 1.2V voltage source. The main topics of this paper are as follows:First, according to the design principles of loop parameter, the design parameters of the filter have been deduced and a design method of the loop parameters based on stability optimization has been proposed.Second, on the basis of analyzing and establishing of equivalent noise model of CPPLL and the impact of each module generating, the noise performance of whole CPPLL has been estimated, furthermore, the result has been simulated and verified by MATLAB.Subsequently, the circuit and layout design of the whole PLL has been completed. In this part, the cause of the dead zone in Phase Frequency Detector (PFD) has been analyzed, and an improvement has been made to the related circuit with method of delay, which quickens the speed of PFD, and reduces the range of dead zone as well as lowers power consumption. Moreover, a Charge-Pump (CP) with voltage follower has been designed to eliminate overshoot and charge-sharing problems in order to improve the stability of the whole system. Besides, a Voltage-Controlled Oscillator (VCO) in which differential amplifier is used as a delay unit has been produced, and it can suppress noise and enhance gain. In addition, a second-order low-pass filter has been adopted in the design, which has a simple structure and occupies small chip area, so that circuit noise and power consumption have been improved. Finally, the overall performance of PLL has been simulated and the properties of the PLL are as follows: lock time is less than 5 ? s, and the VCO jitter of 1KHZ is less than 10ps. Comparison with the results of system behavior-level simulation shows: results of circuit simulation are consistent with that of behavior-level simulation, and behavioral models can guide the circuit design, in order to achieve the design goals and requirements.