Low-jitter Clock Stability Circuit Research And Design

Analog-to-Digital converters (ADCs) are of importance in modern VLSI digital signal processing systems, while Sample and Hold (S/H) circuit is the key front-end block of ADCs. When the resolution of ADCs is above 12bit, the Aperture Uncertainty which can be affected by clock signal will cause the sampling dots shift, thus SNR of S/H circuit will decrease, which will affect the resolution of S/H circuit, and the performance of the whole ADC will be affected as well. So a clock stabilizing circuit is necessary for a more accurate clock on chip to reduce Aperture Uncertainty.A clock stabilizing circuit based on Phase-Locked-Loop is studied and designed in this thesis. It will be applied for a 12bit 100MSample/s ADC, providing clock signals of 100MHz and 50% duty cycle.Based on SMIC 0.18μm CMOS mixed-signal process, the key modules, including PFD, CP, LPF, VCO and divider are designed. Compared with the conventional PFD, which has a "dead zone", the precharge PFD's "dead zone" is eliminated absolutely. The full differential charge pump whose switch is at the sourse has well matching charge and discharge currents, with a mismatch not above 1%.At the same time, charge sharing and clock feedthrough effects existed in conventional charge pump are attenuated in this full differential charge pump. Within the adjusting range, the VCO has a pretty good linearity and the center oscillating frequency is 400MHz.The simulation results of the whole clock stabilizing circuit show that when the power supply is 1.8V, the temperature is 25℃and with TT model, the locking time of the clock stabilizing circuit based on PLL is 17μs. Adding a 0.5ps rms jitter to the input signal and parallelling the according thermal noise current to the key devices of VCO, we get an output signal with 0.3ps rms jitter, which satisfies the 12bit 100MSample/s ADC's demand of not above 0.33ps for the clock signal's rms jitter. Power dissipation of the whole circuit is 13mW when the power supply is 1.8V. Then, the circuit is simulated separately under different process, supply voltage and temperature. The simulation results show that the circuit can operate well under all these PVT conditions. Considering the devices matching, the circuit symmetry and the protecting of the sensitive devices, layout of the whole clock stabilizing circuit based on PLL has been completed. It has an area of 1200μm×480μm.The research results show that the designed clock stabilizing circuit based on Phase-Locked-Loop has a good performance in locking time, frequency rage, output clock jitter and power consumption, which satisfies the 12bit 100MSample/s ADC's demand for the clock stabilizing circuit.