The Design For Testability And The Circuit Of DSPC50

Since the evolution of integrated circuits has developed to the point where millions of transistors can be integrated on a single chip, the testing of ICs become more and more intractable. Then design of testability came forth. This paper presents the design for testability of DSPC50. In Chapter One, the mainly-used methods of Design for testability are introduced firstly. Then a comparison is made according to their characters and the application scope of each method is determinate. From that we get the whole scheme of Design for testability of DSPC50, which is using boundary scan to improve the board-level testability of the chip and using full-scan in designing the nuclear circuit to reduce the difficulty of testing the chip. Chapter Two detailedly presents the design of the boundary scan testing system which is in accordance with IEEE. 1149. Correspondingly two special-used data registers are added, one of which is the scanning chain register and the other is the child scanning chain control-register. Chapter Three takes example for the high speed 16*16 fixed-point multiplier used in the circuit to introduce the design of functional circuits, the structure of testable circuits and the method of generating testing codes. Since the chip has interior SRAM and it's difficult and slow to test SRAM exteriorly, in Chapter Four we use the technique of BIST in Design of testability of SRAM, which makes it possible to test the memory at normal working speed. The last chapter is the summary of the whole paper. It also presents the originality of the work and the plan of later work. By using Design for testability, we can abridge the contriving period and reduce the cost.