Testability Design Of AVP-DSP Chip

The IC industry is in a high-speed development stage at present.With the increasing integration and complexity of chips,the test difficulty and cost of chips are also increasing,which leads to the traditional test methods can not meet the test requirements of modern integrated circuits.Therefore,how to design a high-efficiency and low-cost test structure is an urgent problem.AVP-DSP is a 32-bit floating-point digital signal processor chip with high performance and low power consumption.Scan test,boundary-scan test and built-in self-test are most widely used testability technologies,which are adopted to design the testability structure of AVP-DSP.Firstly,the digital logic circuits such as CPU core and on-chip peripherals are designed with scan test,and seven scan chains are set up.The insertion of scan chains and the generation of test vectors are realized by using DFT Compiler and Tessent respectively.The test coverage and fault coverage meet the design specifications.Then,a boundary-scan test system is designed for the board level application of the chip.The test system is strictly complied with IEEE1149.1 standard,and can execute eight boundary-scan test instructions,including a RUNMBIST instruction,through which the SRAM test can be started.Finally,a built-in self-test design is adopted for on-chip SRAM test.To overcome the shortcoming that March C+ algorithm can not cover all static faults of SRAM,a new March algorithm,March CSC algorithm,is proposed.The new algorithm can not only completely cover static faults,but also has low test complexity which is only 22 N.In order to solve the problem that the chip needs to test two kinds of SRAMs with different address depths,a new memory built-in self-test architecture is designed.Compared with the traditional MBIST circuit,it is more efficient and costs less area.The testability structure of AVP-DSP almost covers all digital circuit modules,which has the advantages of high fault coverage and small area cost.It provides a strong guarantee for the normal functions of the chip and has a certain engineering practical value.At the same time,the technical means such as March CSC algorithm and new MBIST architecture also have a certain guiding significance for the testability design of the chip.